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PDF KS51850 Data sheet ( Hoja de datos )
| Número de pieza | KS51850 | |
| Descripción | 4-bit single-chip CMOS microcontroller | |
| Fabricantes | Samsung | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de KS51850 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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2 KS51850
51850
OVERVIEW
KS51850, a 4-bit single-chip CMOS microcontroller, consists of the reliable SMCS-51 CPU core with on-chip
ROM and RAM. Eight input pins and 11 output pins provide the flexibility for various I/O requirements. Auto reset
circuit generates reset pulse every certain period, and every halt mode termination time. The KS51850
microcontroller has been designed for use in small system control applications that require a low-power, cost -
sensitive design solution. In addition, the KS51850 has been optimized for remote control transmitter and has
built-in Transistor for I.R.LED drive.
FEATURES
ROM Size
• 1,024 bytes
RAM Size
• 32 nibbles
Instruction Set
• 39 instructions
Instruction Cycle Time
• 13.2 µsec at fxx = 455 kHz
Input Ports
• Two 4-bit ports (24 pins)/one 4-bit, Five1-bit
ports (20 pins)
Four Transmission Frequencies
• fxx/12 (1/4 duty), fxx/12 (1/3 duty), fxx/8 (1/2
duty), and no-carrier frequency
Built-in Transistor for I.R.LED Drive
• IOL1: 210 ma (typical) at VDD = 3V and
VO = 0.4V
Supply Voltage
• 1.8 V-3.6 V (250 kHz ≤ fOSC ≤ 3.9 MHz)
2.2 V-3.6 V (3.9 MHz < fOSC ≤ 6 MHz)
Power Consumption
• Halt mode: 1 µA (maxium)
• Normal mode: 0.5 mA (typical)
Output Ports
• One 4-bit, Seven 1-bit ports (24pins)/One 4-bit,
Five 1-bit ports (20 pins)
Built-in Oscillator
• Crystal/Ceramic resonator
Built-in Reset Circuit
• Power-on reset and auto reset circuit for
generating reset pulse every 13.1072/fxx (288
ms at fxx = 455 kHz)
Operating temperature
• - 20 °C to 85 °C
Package Type
• 24 SOP, 20 DIP, 20 SOP
Oscillator Frequency divide select
• Mask Option = fxx fOSC or fOSC/8
2-1
1 page  
I/O CIRCUIT SCHEMATICS
VDD
30 -150 kΩ
In
VSS
Figure 2-4. I/O Circuit Type A
VDD
Data
Disable(note)
Data
Out
N-CH
TEST
VSS
NOTE: If data disable signal is active, halt mode,
the output becomes floating state.
Figure 2-5. I/O Circuit Type B
51850
VDD
Data
Data
Disable(note)
Out
N-CH
VSS
NOTE: If data disable signal is active, halt mode,
the output becomes low state.
Figure 2-6. I/O Circuit Type C
VDD
Data
Out
N-CH
VSS
Figure 2-7. I/O Circuit Type D
2-5
5 Page 
51850
REGISTER DESCRIPTIONS
Stack Register (SR)
Three levels of subroutine nesting are supported by a three-level stack as shown in Figure 2-13.
Each subroutine call (CALL) pushes the next PA and PC address into the strack. The latest stack to be stored
will be overwritten and lost. Each return instruction (RET) pops the stack back into the PA and PC registers.
SR
PA PC
: Push Operation (CALL)
: Pop Operation (RET)
Figure 2-12. Stack Operations
Page Address Register (PA), Page Buffer Register (PB)
The Page Address Register (PA) and Page Buffer Register (PB) are 4-bit registers. The PA always specifies the
current page.
A page select instruction (PAGE #n) loads the value “n” into the PB. When JP or CALL instruction is executed,
and if the Status Flag (SF) is set to 1, the contents of PB are loaded into PA. If SF is “0”, however, the JP or
CALL is executed like NOP instruction and SF is set to “1”. The contents of PB don’t be loaded. Figure 1-14
illustrates this concept.
4
PB
4
PA
Common Bus
PAGE #n
JP xxx (CALL xxx)
; PB n
; PA PB
if SF = 1
Figure 2-13. PA, PB Operations
2-11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet KS51850.PDF ] | |
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