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PDF AZ10LVEL11 Data sheet ( Hoja de datos )
| Número de pieza | AZ10LVEL11 | |
| Descripción | ECL/PECL 1:2 Differential Fanout Buffer | |
| Fabricantes | Arizona Microtek | |
| Logotipo |  |
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ARIZONA MICROTEK, INC.
AZ10LVEL11
AZ100LVEL11
ECL/PECL 1:2 Differential Fanout Buffer
FEATURES
PACKAGE AVAILABILITY
• 265ps Propagation Delay
• 5ps Skew Between Outputs
• High Bandwidth Output Transitions
• Internal Input Pulldown Resistors
• Operating Range of 3.0V to 5.5V
• Direct Replacement for ON Semi
MC100LVEL11, MC10EL11
& MC100EL11
• Transistor Count = 51
DESCRIPTION
PACKAGE
PART NUMBER MARKING NOTES
SOIC 8
AZ10LVEL11D
AZM10
LVEL11
1,2
SOIC 8
AZ100LVEL11D
AZM100
LVEL11
1,2
SOIC 8 RoHS
Compliant / Lead
(Pb) Free
AZ10LVEL11D+
AZM10+
LVEL11
1,2
SOIC 8 RoHS
Compliant / Lead
(Pb) Free
AZ100LVEL11D+
AZM100+
LVEL11
1,2
TSSOP 8
AZ10LVEL11T
AZT
LV11
1,2
TSSOP 8
AZ100LVEL11T
AZH
LV11
1,2
TSSOP 8 RoHS
Compliant / Lead
(Pb) Free
AZ100LVEL11T+
AZH+
LV11
1,2
1 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Tape & Reel.
2 Date code “YWW” or “YYWW” on underside of part.
The AZ10/100LVEL11 is a differential 1:2 fanout gate. The device is functionally similar to the E111 device
but with higher performance capabilities. Having within-device skews and output transition times significantly
improved over the E111, the AZ10/100LVEL11 is ideally suited for those applications that require the ultimate in
AC performance.
The differential inputs of the AZ10/100LVEL11 employ clamping circuitry to maintain stability under open
input conditions. If the inputs are left open, the Q outputs will go LOW.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
PIN DESCRIPTION
PIN
D, D¯
Q0, Q¯¯0, Q1, Q¯¯1
VCC
VEE
FUNCTION
Data Inputs
Data Outputs
Positive Supply
Negative Supply
Q0 1
Q0 2
Q1 3
8 VCC
7D
6D
Q1 4
5 VEE
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com
1 page  
AZ10LVEL11
AZ100LVEL11
PACKAGE DIAGRAM
SOIC 8
NOTES:
1. DIMENSIONS D AND E DO NOT
INCLUDE MOLD PROTRUSION.
2. MAXIMUM MOLD PROTRUSION
FOR D IS 0.15mm.
3. MAXIMUM MOLD PROTRUSION
FOR E IS 0.25mm.
DIM
A
A1
A2
A3
bp
c
D
E
e
HE
L
Lp
Q
v
w
y
Z
θ
MILLIMETERS
MIN MAX
1.75
0.10 0.25
1.25 1.45
0.25
0.36 0.49
0.19 0.25
4.8 5.0
3.8 4.0
1.27
5.80 6.20
1.05
0.40 1.00
0.60 0.70
0.25
0.25
0.10
0.30 0.70
0O 8O
INCHES
MIN MAX
0.069
0.004 0.010
0.049 0.057
0.01
0.014 0.019
0.0075 0.0100
0.19 0.20
0.15 0.16
0.050
0.228 0.244
0.041
0.016 0.039
0.024 0.028
0.01
0.01
0.004
0.012
0O
0.028
8O
June 2007 * REV - 3
www.azmicrotek.com
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet AZ10LVEL11.PDF ] | |
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