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AZ100LVEL16VV 데이터시트 PDF




Arizona Microtek에서 제조한 전자 부품 AZ100LVEL16VV은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 AZ100LVEL16VV 자료 제공

부품번호 AZ100LVEL16VV 기능
기능 Dual Frequency ECL/PECL Oscillator Gain Stage & Buffer
제조업체 Arizona Microtek
로고 Arizona Microtek 로고


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AZ100LVEL16VV 데이터시트, 핀배열, 회로
www.DataSheet4U.com
ARIZONA MICROTEK, INC.
AZ100LVEL16VV
Dual Frequency ECL/PECL Oscillator Gain Stage & Buffer with Enable
FEATURES
PACKAGE AVAILABILITY
High Bandwidth for 1GHz
Similar Operation as AZ100EL16VR
except with selectable data input pairs
Operating Range of 3.0V to 5.5V
Minimizes External Components
Available in a 3x3mm MLP Package
S–Parameter (.s2p) and IBIS Model
Files Available on Arizona
Microtek Website
PACKAGE
PART NUMBER MARKING NOTES
MLP 16 (3x3) RoHS
AZM+
Compliant / Lead (Pb) AZ100LVEL16VVL+ 16K
1,2
Free <Date Code>
DIE
AZ100LVEL16VVXP N/A
3
1 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape
& Reel.
2 Date code format: “Y” for year followed by “WW” for week.
3 Waffle Pack
DESCRIPTION
The AZ100LVEL16VV is a specialized oscillator gain stage with two selectable data input pairs and a high gain
output buffer including an enable. The QHG/Q¯ HG outputs have a voltage gain several times greater than the Q/Q¯
outputs.
The AZ100LVEL16VV provides two selectable data input pairs that permit switching between two different
oscillator frequencies. When the select pin (SEL) is LOW or open (NC) data from the D0/D¯¯0 is selected. When the
SEL pin is HIGH data from the D1/D¯¯1 is selected. Allowing continuous oscillator operation, the (EN) enable works
with either data input pair. When EN is HIGH or open (NC), input data is passed to both sets of outputs. When EN
is LOW, the QHG/Q¯ HG outputs will be forced LOW/HIGH respectively, while input data will continue to be passed to
the Q/Q¯ outputs. The EN and SEL inputs can be driven with an ECL/PECL signal or a full supply swing CMOS
type logic signal.
The AZ100LVEL16VV also provides a VBB with a 1.5mA sink/source current. Each data input is separately
connected to VBB with a 470Ω internal bias resistor. Bypassing VBB to ground with a 0.01 μF capacitor is
recommended.
Each Q/Q¯ output has a 4 mA on-chip pull-down current source. External resistors may also be used to increase
pull-down current of the Q/Q¯ to a maximum of 25mA each (includes a 4 mA on-chip current source).
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
1630 S. STAPLEY DR., SUITE 127 MESA, ARIZONA 85204 USA (480) 962-5881 FAX (480) 890-2541
www.azmicrotek.com




AZ100LVEL16VV pdf, 반도체, 판매, 대치품
AZ100LVEL16VV
1 0.00
0.95 -5.00
0.9 -10.00
0.85 -15.00
0.8 -20.00
0.75 -25.00
0.7
50
-30.00
150 250 350 450 550 650 750 850 950 1050 1150 1250 1350
Frequency (MHz)
S11 MAG
S11 PHASE
S11, D0/D1 to Q¯ , 50 Ω AC load on Q¯
0.02 250.00
0.0175
225.00
0.015
200.00
0.0125
175.00
0.01 150.00
0.0075
125.00
0.005
100.00
0.0025
75.00
0 50.00
50 150 250 350 450 550 650 750 850 950 1050 1150 1250 1350
Frequency (MHz)
S12 MAG
S12 PHASE
S12, D0/D1 to Q¯ , 50 Ω AC load on Q¯
April 2007 * REV - 9
www.azmicrotek.com
4

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AZ100LVEL16VV 전자부품, 판매, 대치품
AZ100LVEL16VV
AZ100LVEL16VV DIE:
EL16VV
A
M
LK
B DIE SIZE: 950u X 940u
DIE THICKNESS: 14 mils
C
BOND PAD: 85u X 85u
J
I
H
DG
EF
PAD COORDINATES1
NAME
A
B
C
D
E
F
G
H
I
J
K
L
M
1. 0, 0 is center of die.
PAD DESIGNATION
D0
D¯¯0
D1
D¯¯1
VBB
VEE
EN
HG
QHG
SEL
VCC
Q
PAD CENTERS
X(Microns)
Y(Microns)
-342.5
312.5
-342.5
144.5
-342.5
-87.0
-342.5
-255.0
-33.5
-312.5
126.5
-312.5
312.5
-248.5
312.5
-98.5
312.5
51.5
312.5
201.5
302.5
342.5
142.5
342.5
-140.5
342.5
April 2007 * REV - 9
www.azmicrotek.com
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