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AZ100LVE111 데이터시트 PDF




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부품번호 AZ100LVE111 기능
기능 ECL/PECL 1:9 Differential Clock Driver
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AZ100LVE111 데이터시트, 핀배열, 회로
www.DataSheet4U.com
ARIZONA MICROTEK, INC.
AZ10LVE111
AZ100LVE111
ECL/PECL 1:9 Differential Clock Driver
FEATURES
Operating Range of 3.0V to 5.5V
Low Skew
Guaranteed Skew Spec
Differential Design
VBB Output
75kΩ Internal Pulldown Resistors
Direct Replacement for ON
Semiconductor MC100LVE111
DESCRIPTION
PACKAGE AVAILABILITY
PACKAGE
PART NO.
MARKING NOTES
PLCC 28
AZ10LVE111FN
AZ10
LVE111
<Date Code>
1,2
PLCC 28
AZ100LVE111FN
AZ100
LVE111
<Date Code>
1,2
PLCC 28 RoHS
Compliant / Lead
(Pb) Free
AZ100LVE111FN+
AZ100+
LVE111
<Date Code>
1,2
1 Add R2 at end of part number for 13 inch (750 parts) Tape & Reel.
2 Date code format: “YY” for year followed by “WW” for week.
The AZ10/100LVE111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. The
IN signal is fanned-out to nine identical differential outputs.
The AZ100LVE111 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the
device. For single–ended input applications, the VBB reference should be connected to one side of the IN/I¯N¯
differential input pair. The input signal is then fed to the other IN/I¯N¯ input. When used, the VBB pin should be
bypassed to ground via a 0.01μF capacitor.
The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design and
layout serve to minimize gate-to-gate skew within-device, and empirical modeling is used to determine process
control limits that ensure consistent tpd distributions from lot-to-lot. The net result is a dependable, guaranteed low
skew device.
To ensure that the tight skew specification is met, both sides of the differential output must be terminated into
50Ω, even if only one side is used. In most applications all nine differential pairs will be used and therefore
terminated. In the case where fewer than nine pairs are used, it is necessary to terminate at least the output pairs on
the same package side (i.e. sharing the same VCCO) as the pair(s) being used on that side, in order to maintain
minimum skew. Failure to do this will result in small degradations of propagation delay (on the order of 10-20ps) of
the output(s) being used that, while not being catastrophic to most designs, will mean a loss of skew margin.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
1630 S. STAPLEY DR., SUITE 127 MESA, ARIZONA 85204 USA (480) 962-5881 FAX (480) 890-2541
www.azmicrotek.com




AZ100LVE111 pdf, 반도체, 판매, 대치품
AZ10LVE111
AZ100LVE111
100K PECL DC Characteristics (VEE = GND, VCC = VCCO = +5.0V)
Symbol
Characteristic
-40°C
0°C
Min Typ Max Min Typ Max Min
VOH Output HIGH Voltage1,2 3915 3995 4120 3975 4045 4120 3975
VOL
Output LOW Voltage1,2
3170 3305 3445 3190 3295 3380 3190
VIH
Input HIGH Voltage1
3835
4120 3835
4120 3835
VIL Input LOW Voltage1 3190
3525 3190
3525 3190
VBB Reference Voltage1
3620
3740 3620
3740 3620
IIH Input HIGH Current
150 150
IIL Input LOW Current
0.5
0.5
0.5
IEE Power Supply Current
48 60
48 60
1. For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value.
2. Each output is terminated through a 50Ω resistor to VCC – 2V.
25°C
Typ
4045
3295
Max
4120
3380
4120
3525
3740
150
48 60
Min
3975
3190
3835
3190
3620
0.5
85°C
Typ
4045
3295
55
Max
4120
3380
4120
3525
3740
150
69
Unit
mV
mV
mV
mV
mV
μA
μA
mA
AC Characteristics (VEE = -3.0V to -5.5V, VCC = VCCO = GND or VEE = GND, VCC = VCCO = +3.0 to +5.5V)
Symbol
Characteristic
-40°C
0°C
25°C
85°C
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
tPLH / tPHL
Propagation Delay
to Output IN (Diff)1
IN (SE)2
380
280
650 460
700 410
560 480
610 430
580 510
630 460
610
660
tskew Within-Device Skew3
VPP (AC) Minimum Input Swing4
25
250
75 25
250
50 25
250
50 25
250
50
VCMR
Common Mode Range5
VEE +
1.8
VCC - VEE +
0.4 1.8
VCC - VEE +
0.4 1.8
VCC - VEE +
0.4 1.8
VCC -
0.4
tr / tf Rise/Fall Time
250 650 275 600 275 600 275 600
1. The differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the
differential output signals.
2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
3. The within-device skew is defined as the worst-case difference between any two similar delay paths within a single device.
4. VPP is the minimum peak-to-peak differential input swing for which AC parameters are guaranteed. The VPP(min) is AC limited for the LVE111,
because differential input as low as 50 mV will still produce full ECL levels at the output.
5. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level
must be such that the peak-to-peak voltage is less than 1.0 V and greater than or equal to VPP(min).
Unit
ps
ps
mV
V
ps
November 2006 * REV - 5
www.azmicrotek.com
4

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부품번호상세설명 및 기능제조사
AZ100LVE111

ECL/PECL 1:9 Differential Clock Driver

Arizona Microtek
Arizona Microtek
AZ100LVE111

ECL/PECL 1:9 Differential Clock Driver

Arizona Microtek
Arizona Microtek

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