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PDF AZP92 Data sheet ( Hoja de datos )
| Número de pieza | AZP92 | |
| Descripción | Clock Generation Chip | |
| Fabricantes | Arizona Microtek | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AZP92 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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AZP92
ARIZONA MICROTEK, INC.
ECL/PECL ÷1, ÷2 Clock Generation Chip with Selectable Enable
FEATURES
PACKAGE AVAILABILITY
• Green and RoHS Compliant / Lead (Pb) PACKAGE
PART NO.
Free Package Available
• 3.0V to 5.5V Operation
MLP 8 (2x2) Green
/ RoHS Compliant AZP92NAG
• Selectable Divide Ratio
/ Lead (Pb) Free
MARKING
P1G
<Date Code>
NOTES
1,2
• Selectable Enable Polarity and
DIE
AZP92X
N/A
3,4
Threshold (CMOS/TTL or PECL)
• Selectable Input Biasing
1 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Tape & Reel.
• High Bandwidth for ≥1GHz
2 Date code format: “Y” for year followed by “WW” for week.
• Available in a MLP 8 (2x2) Package
• IBIS Model File Available on Arizona
3 Waffle Pack
4 Contact factory for availability
Microtek Website
DESCRIPTION
The AZP92 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function. The divide ratio is
selected with the DIV-SEL pin/pad. When DIV-SEL is open (NC), the AZP92 functions as a standard receiver. If
DIV-SEL is connected to VEE, it functions as a ÷2 divider.
A selectable enable is provided which also functions as a reset when the ÷2 mode is selected. Enable (EN)
functionality is selected with the EN-SEL pin/pad which has three valid states: open (NC), VEE, or connected to VEE
via a 20kΩ resistor. Leaving EN-SEL open or connecting it to VEE will select the EN pin/pad to function as an active
high CMOS/TTL enable. When EN-SEL is open, an internal 75kΩ pull-up resistor is selected which enables the
outputs whenever EN is left open. When EN-SEL is connected to VEE, an internal 75kΩ pull-down resistor is
selected which disables the outputs whenever EN is left open.
Connecting the EN-SEL to VEE with a 20kΩ resistor will select the EN pin/pad to function as an active low
PECL/ECL enable with an internal 75kΩ pull-down resistor. In this mode, outputs are enabled when EN is left open
(NC). This default logic condition can be overridden by connecting the EN to VCC with an external resistor of
≤20kΩ. Refer to the enable truth table on the next page for detailed operation.
DIE (AZP92X)
The AZP92X provides a VBB and a BIAS pad with 940Ω internal resistors from D to BIAS and D¯ to BIAS.
Connecting the BIAS pad to VBB allows D and D¯ to be AC coupled with minimal external components. For single
ended applications, D or D¯ may be connected directly to VBB to form a single 1880Ω bias resistor. The VBB pin
supports 1.5mA sink/source current. Whenever used, the VBB should be bypassed to ground or VCC with a 0.01 μF
capacitor.
MLP 8, 2x2 mm Package (AZP92NA)
The AZP92NA provides a VBB with an 1880Ω internal bias resistor from D to VBB. This feature allows AC
coupling with minimal external components. The VBB pin supports 1.5mA sink/source current and should be
bypassed to ground or VCC with a 0.01 μF capacitor.
NOTE: The specifications in the ECL/PECL tables are valid when thermal equilibrium has been established.
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com
1 page  
AZP92
100K PECL DC Characteristics (VEE = GND, VCC = +5.0V)
Symbol
Characteristic
-40°C
Min Max
0°C
Min Max
25°C
Min Max
VOH Output HIGH Voltage1,2
3915
4120
3975
4120
3975
4120
VOL Output LOW Voltage1,2
3100
3445
3100
3380
3100
3380
Input HIGH Voltage1
VIH
D/D¯ , EN (PECL)3 3835
4610
3835
4610
3835
4610
EN (CMOS)4 2000 VCC 2000 VCC 2000 VCC
Input LOW Voltage1
VIL
D/D¯ , EN (PECL)3 2750
3525
2750
3525
2750
3525
EN (CMOS)4 GND 800 GND 800 GND 800
VBB Reference Voltage1
3610
3750
3610
3750
3610
3750
IIH Input HIGH Current EN 150 150 150
Input LOW Current
IIL
EN (PECL)3
0.5
0.5
0.5
EN (CMOS)4
-150
-150
-150
IEE Power Supply Current5
31 31
31
1. For supply voltages other that 5.0V, use the ECL table values and ADD supply voltage value.
2. Specified with outputs terminated through 50Ω resistors to VCC - 2V.
3. EN-SEL connected to VEE through a 20kΩ resistor.
4. EN-SEL connected VEE or left open (NC).
5. DIV-SEL left open (NC).
85°C
Min Max
3975
4120
3100
3380
3835
2000
2750
GND
3610
4610
VCC
3525
800
3750
150
0.5
-150
34
Unit
mV
mV
mV
mV
mV
μA
μA
mA
AC Characteristics (VEE = -3.0V to -5.5V; VCC = GND or VEE = GND; VCC = +3.0V to +5.5V)
Symbol
Characteristic
-40°C
0°C
25°C
85°C
Unit
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
tPLH / tPHL
tSKEW
Propagation Delay
D to Q/Q¯ Outputs1
EN to Q/Q¯ Outputs1
Duty Cycle Skew2
Input Swing3
(SE)
(SE)
450
600
5 20
450
600
5 20
450
600
5 20
450 ps
600
5 20 ps
VPP (AC)
tr / tf
Differential (D/D¯ )
Single Ended (D)4
Output Rise/Fall1
(20% - 80%)
150
300
80
1000
2000
200
150
300
80
1000
2000
200
150
300
80
1000
2000
200
150
300
80
1000
2000
200
mV
ps
1. Specified with outputs terminated through 50Ω resistors to VCC - 2V.
2. Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device.
3. The peak-to-peak input swing is the range for which AC parameters are guaranteed.
4. Range valid for AC coupled signals only.
AC PP INPUT (Differential)
D
D
VPP (AC)
April 2007 REV - 3
www.azmicrotek.com
5
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| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet AZP92.PDF ] | |
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