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STK11C88 데이터시트 PDF




Simtek에서 제조한 전자 부품 STK11C88은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 STK11C88 자료 제공

부품번호 STK11C88 기능
기능 32Kx8 SoftStore nvSRAM
제조업체 Simtek
로고 Simtek 로고


STK11C88 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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STK11C88 데이터시트, 핀배열, 회로
www.DataSheet4U.com
FEATURES
• 25, 45 ns Read Access & R/W Cycle Time
• Unlimited Read/Write Endurance
• Pin Compatible with Industry Standard SRAMs
• Software-initiated STORE and RECALL
• Automatic RECALL to SRAM on Power Up
• Unlimited RECALL Cycles
• 1 Million Store Cycles
• 100-Year Non-volatile Data Retention
• Single 5V ± 10% Power Supply
• Commercial and Industrial Temperatures
• 28-pin 300-mil and 330-mil SOIC Packages
(RoHS-Compliant)
DESCRIPTION
STK11C88
32Kx8 SoftStore nvSRAM
The Simtek STK11C88 is a 256Kb fast static RAM
with a non-volatile Quantum Trap storage element
included with each memory cell.
The SRAM provides the fast access & cycle times,
ease of use and unlimited read & write endurance of
a normal SRAM.
Data transfers under software control to the non-vol-
atile storage cell (the STORE operation). On power
up, data is automatically restored to the SRAM (the
RECALL operation). RECALL operations are also
available under software control.
The Simtek nvSRAM is the first monolithic non-
volatile memory to offer unlimited writes and reads.
It is the highest performance, most reliable non-
volatile memory available.
BLOCK DIAGRAM
A5
A6
A7
A8
A9
A11
A12
A13
A14
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
QUANTUM TRAP
512 x 512
STATIC RAM
ARRAY
512 X 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
This product conforms to specifications per the
terms of Simtek standard warranty. The product
has completed Simtek internal qualification testing
and has reached production status.
1
STORE/
RECALL
CONTROL
SOFTWARE
DETECT
A13 – A0
G
E
W
Document Control #ML0012 Rev 0.3
February 2007




STK11C88 pdf, 반도체, 판매, 대치품
STK11C88
SRAM READ CYCLES #1 & #2
SYMBOLS
NO. #1, #2
Alt.
PARAMETER
1 tELQV
2 tAVAVf
3 tAVQVg
tACS
tRC
tAA
4 tGLQV
5 tAXQXg
tOE
tOH
6 tELQX
7 tEHQZh
tLZ
tHZ
8 tGLQX
tOLZ
9 tGHQZh
tOHZ
10 tELICCHe
tPA
11
tEHICCLd, e
tPS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected.
Note h: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledf, g
ADDRESS
DQ (DATA OUT)
5
tAXQX
2
tAVAV
3
tAVQV
SRAM READ CYCLE #2: E Controlledf
ADDRESS
E
6
tELQX
2
tAVAV
1
tELQV
DATA VALID
(VCC = 5.0V + 10%)
STK11C88-25 STK11C88-45
UNITS
MIN MAX MIN MAX
25 45 ns
25 45 ns
25 45 ns
10 20 ns
5 5 ns
5 5 ns
10 15 ns
0 0 ns
10 15 ns
0 0 ns
25 45 ns
11
tEHICCL
7
tEHQZ
G
DQ (DATA OUT)
ICC
4
8 tGLQV
tGLQX
10
tELICCH
STANDBY
ACTIVE
9
tGHQZ
DATA VALID
Document Control #ML0012 Rev 0.3
February 2007
4

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STK11C88 전자부품, 판매, 대치품
SOFTWARE STORE/RECALL MODE SELECTION
STK11C88
EW
LH
A13 - A0 (hex)
0E38
31C7
03E0
3C1F
303F
0FC0
MODE
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
I/O
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
NOTES
m, n
LH
0E38
31C7
03E0
3C1F
303F
0C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
m, n
Note l: The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
Note m: While there are 15 addresses on the STK11C88, only the lower 14 are used to control software modes.
SOFTWARE STORE/RECALL CYCLEn, o
(VCC = 5.0V ± 10%)
NO. SYMBOLS
PARAMETER
STK11C88-25
MIN MAX
STK11C88-45
MIN MAX
UNITS
26 tAVAV
STORE/RECALL Initiation Cycle Time
27 tAVELn
Address Set-up Time
28 tELEHn
Clock Pulse Width
29 tELAXn
Address Hold Time
30 tRECALLn RECALL Duration
25 45 ns
0 0 ns
20 30 ns
20 20 ns
20 20 μs
Note n:
Note o:
The software sequence is clocked with E controlled reads.
The six consecutive addresses must be in the order listed in the Software STORE/RECALL Mode Selection Table: (0E38, 31C7, 03E0, 3C1F,
303F, 0FC0) for a STORE cycle or (0E38, 31C7, 03E0, 3C1F, 303F, 0C63) for a RECALL cycle. W must be high during all six consecutive
cycles.
SOFTWARE STORE/RECALL CYCLE: E Controlledo
ADDRESS
26
tAVAV
ADDRESS #1
26
tAVAV
ADDRESS #6
27
tAVEL
28
tELEH
E
DQ (DATA
29
tELAX
DATA VALID
/23 30
tSTORE tRECALL
DATA VALID
HIGH IMPEDANCE
Document Control #ML0012 Rev 0.3
February 2007
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