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PDF LNBP21PD-TR Data sheet ( Hoja de datos )
| Número de pieza | LNBP21PD-TR | |
| Descripción | LNBP SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACE | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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LNBP21
LNBP SUPPLY AND CONTROL IC WITH
STEP-UP CONVERTER AND I2C INTERFACE
s COMPLETE INTERFACE BETWEEN LNB
AND I2CTM BUS
s BUILT-IN DC/DC CONTROLLER FOR
SINGLE 12V SUPPLY OPERATION
s ACCURATE BUILT-IN 22KHz TONE
OSCILLATOR
s SUITS WIDELY ACCEPTED STANDARDS
s FAST OSCILLATOR START-UP FACILITATES
DiSEqCTM ENCODING
s BUILT-IN 22KHz TONE DETECTOR
SUPPORTS BI-DIRECTIONAL DiSEqCTM
s LOOP-THROUGH FUNCTION FOR SLAVE
OPERATION
s LNB SHORT CIRCUIT PROTECTION AND
DIAGNOSTIC
s CABLE LENGTH DIGITAL COMPENSATION
s INTERNAL OVER TEMPERATURE
PROTECTION
s ESD RATING 4KV ON POWER
INPUT-OUTPUT PINS
PowerSO-20
SO-20
DESCRIPTION
Intended for analog and digital satellite STB
receivers/SatTV, sets/PC cards, the LNBP21 is a
monolithic voltage regulator and interface IC,
assembled in SO-20 and PowerSO-20,
specifically designed to provide the power and the
13/18V, 22KHz tone signalling to the LNB
SCHEMATIC DIAGRAM
Gate
Sense
LNBP21
Step-up
Controller
Feedback
Vup
Vcc
Byp
Preregul.+
U.V.lockout
+P.ON res.
SDA
SCL
ADDR
DSQIN
I²C
interf.
Enable
I Select
V Select
Linear Post-reg
+Modulator
+Protections
Diagnostics
22KHz
Oscill.
Tone
Detector
LT1
LT2
OUT
EXTM
DETIN
DSQOUT
October 2002
1/20
1 page  
LNBP21
TYPICAL APPLICATION CIRCUIT
IC2
(Note 3)
L1=22µH
Vin
12V
C2
220µF
STS4DNFS30L
Rsc
0.1Ω (Note 4)
C1
220µF
D1 1N4001
IC1
C3
470nF
Ceramic
Vup
Master STB
LT1
C7
10nF
C4
470nF
Ceramic
Gate
Sense
Vcc
LT2
LNBP21
Vo
C8
10nF
DETIN
(Note 1)
Byp
270µH
D2
BAT43
15 ohm
see Note 2
C6
10nF
C5
470nF
to LNB
DSQIN(Note 1)
SCL
SDA
GND
EXTM
ADDRESS
DSQOUT
0<Vaddr<VByp
(*) Set to GND if not used
(**) filter to be used according to EUTELSAT reccomendation to implement the DiSEqCTM 2.x, not needed if bidirectional DiSEqCTM 2.x is
not implemented (see DiSEqC implementation note)
(***) IC2 is a ST Fettky, STS4DNFS30L, that includes both the schottky diode and the N-Channel Mos-Fet, needed for the DC/DC converter,
in a So-8 package. It can be replaced by a schottky diode (STPS2L3A or similar) and a N-Channel Mos-Fet (STN4NF03L or similar)
I2C BUS INTERFACE
Data transmission from main µP to the LNBP21
and viceversa takes place through the 2 wires I2C
bus interface, consisting of the two lines SDA and
SCL (pull-up resistors to positive supply voltage
must be externally connected).
DATA VALIDITY
As shown in fig. 1, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
START AND STOP CONDITIONS
As shown in fig.2 a start condition is a HIGH to
LOW transition of the SDA line while SCL is HIGH.
The stop condition is a LOW to HIGH transition of
the SDA line while SCL is HIGH. A STOP
condi-tions must be sent before each START
condition.
BYTE FORMAT
Every byte transferred to the SDA line must
contain 8 bits. Each byte must be followed by an
ac-knowledge bit. The MSB is transferred first.
ACKNOWLEDGE
The master (µP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 3). The peripheral (LNBP21) that
acknowledges has to pull-down (LOW) the SDA
line during the acknowledge clock pulse, so that
the SDA line is stable LOW during this clock pulse.
The peripheral which has been addressed has to
generate an acknowledge after the reception of
each byte, other-wise the SDA line remains at the
HIGH level during the ninth clock pulse time. In
this case the master transmitter can generate the
STOP information in order to abort the transfer.
The LNBP21 won't gen-erate the acknowledge if
the Vcc supply is below the Undervoltage Lockout
threshold (6.7V typ.).
TRANSMISSION WITHOUT ACKNOWLEDGE
Avoiding to detect the acknowledge of the
LNBP21, the µP can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.
This approach of course is less protected from
misworking and decreases the noise immunity.
5/20
5 Page 
LNBP21
TYPICAL CHARACTERISTICS (unless otherwise specified Tj = 25°C)
Figure 4 : Output Voltage vs Temperature
Figure 7 : Line Regulation vs Temperature
Figure 5 : Output Voltage vs Temperature
Figure 8 : Load Regulation vs Temperature
Figure 6 : Line Regulation vs Temperature
Figure 9 : Load Regulation vs Temperature
11/20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet LNBP21PD-TR.PDF ] | |
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