|
|
PDF LNBS21 Data sheet ( Hoja de datos )
| Número de pieza | LNBS21 | |
| Descripción | LNB SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACE | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de LNBS21 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
|
No Preview Available !
LNBS21
LNB SUPPLY AND CONTROL IC WITH
STEP-UP CONVERTER AND I2C INTERFACE
s COMPLETE INTERFACE BETWEEN LNB
AND I2CTM BUS
s BUILT-IN DC/DC CONTROLLER FOR
SINGLE 12V SUPPLY OPERATION
s ACCURATE BUILT-IN 22KHz TONE
OSCILLATOR
s SUITS WIDELY ACCEPTED STANDARDS
s FAST OSCILLATOR START-UP FACILITATES
DiSEqCTM ENCODING
s BUILT-IN 22KHz TONE DETECTOR
SUPPORTS BI-DIRECTIONAL DiSEqCTM
s LOOP-THROUGH FUNCTION FOR SLAVE
OPERATION
s LNB SHORT CIRCUIT PROTECTION AND
DIAGNOSTIC
s CABLE LENGTH DIGITAL COMPENSATION
s INTERNAL OVER TEMPERATURE
PROTECTION
DESCRIPTION
Intended for analog and digital satellite STB
receivers/SatTV, sets/PC cards, the LNBS21 is a
monolithic voltage regulator and interface IC,
SCHEMATIC DIAGRAM
PowerSO-20
assembled in PowerSO-20, specifically designed
to provide the power and the 13/18V, 22KHz tone
signalling to the LNB downconverter in the
antenna or to the multiswitch box. In this
application field, it offers a complete solution with
extremely low component count, low power
dissipation together with simple design and I2CTM
standard interfacing.
This IC has a built in DC/DC step-up controller
that, from a single supply source ranging from 8 to
15V, generates the voltages that let the linear
Gate
Sense
LNBS21
Step-up
Controller
Feedback
Vup
Vcc
Byp
Preregul.+
U.V.lockout
+P.ON res.
SDA
SCL
ADDR
DSQIN
I²C
interf.
Enable
I Select
V Select
Linear Post-reg
+Modulator
+Protections
Diagnostics
22KHz
Oscill.
Tone
Detector
LT1
LT2
OUT
EXTM
DETIN
DSQOUT
November 2002
1/19
1 page  
LNBS21
TYPICAL APPLICATION CIRCUIT
Schottky
diode
STPS3L40S
or 1N5821
L1=22µH
Vin
12V
C2
220µF
IC1
C3
470nF
Ceramic
Vup
D1 1N4001
LT1
LT2
MOSFET
STN4NF03L
Rsc
0.05Ω
C1
220µF
C4
470nF
Ceramic
Gate
Sense
LNBS21
Vout
C8
10nF
DETIN(*)
Vcc
DSQIN(*)
SCL
SDA
Byp
GND
EXTM
ADDRESS
DSQOUT
Master STB
C7
10nF
270µH
D2
BAT43
15 ohm
(**) see note
C6
10nF
C5
470nF
0<Vaddr<VByp
to LNB
(*) Set to GND if not used
(**) filter to be used according to EUTELSAT reccomendation to implement the DiSEqCTM 2.0, not needed if bidirectional DiSEqCTM 2.0 is
not implemented (see DiSEqC implementation note)
I2C BUS INTERFACE
Data transmission from main µP to the LNBS21
and viceversa takes place through the 2 wires I2C
bus interface, consisting of the two lines SDA and
SCL (pull-up resistors to positive supply voltage
must be externally connected).
DATA VALIDITY
As shown in fig. 1, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
START AND STOP CONDITIONS
As shown in fig.2 a start condition is a HIGH to
LOW transition of the SDA line while SCL is HIGH.
The stop condition is a LOW to HIGH transition of
the SDA line while SCL is HIGH. A STOP
condi-tions must be sent before each START
condition.
BYTE FORMAT
Every byte transferred to the SDA line must
contain 8 bits. Each byte must be followed by an
ac-knowledge bit. The MSB is transferred first.
ACKNOWLEDGE
The master (µP) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 3). The peripheral (LNBS21) that
acknowledges has to pull-down (LOW) the SDA
line during the acknowledge clock pulse, so that
the SDA line is stable LOW during this clock pulse.
The peripheral which has been addressed has to
generate an acknowledge after the reception of
each byte, other-wise the SDA line remains at the
HIGH level during the ninth clock pulse time. In
this case the master transmitter can generate the
STOP information in order to abort the transfer.
The LNBS21 won't gen-erate the acknowledge if
the Vcc supply is below the Undervoltage Lockout
threshold (6.7V typ.).
TRANSMISSION WITHOUT ACKNOWLEDGE
Avoiding to detect the acknowledge of the
LNBS21, the µP can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.
This approach of course is less protected from
misworking and decreases the noise immunity.
5/19
5 Page 
LNBS21
TYPICAL CHARACTERISTICS (unless otherwise specified Tj = 25°C)
Figure 4 : Output Voltage vs Temperature
Figure 7 : Line Regulation vs Temperature
Figure 5 : Output Voltage vs Temperature
Figure 8 : Load Regulation vs Temperature
Figure 6 : Line Regulation vs Temperature
Figure 9 : Load Regulation vs Temperature
11/19
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet LNBS21.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| LNBS21 | LNB SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACE | STMicroelectronics |
| LNBS21PD | LNB SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACE | STMicroelectronics |
| LNBS21PD-TR | LNB SUPPLY AND CONTROL IC WITH STEP-UP CONVERTER AND I2C INTERFACE | STMicroelectronics |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |