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Número de pieza | LXT972M | |
Descripción | Single-Port 10/100 Mbps PHY Transceiver | |
Fabricantes | Intel Corporation | |
Logotipo | ||
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Intel® LXT972M Single-Port 10/100 Mbps
PHY Transceiver
Datasheet
The Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver is an IEEE compliant Fast
Ethernet PHY Transceiver that directly supports both 100BASE-TX and 10BASE-T applications. It
provides a Media Independent Interface (MII) for easy attachment to 10/100 Media Access
Controllers (MACs). Both full and half-duplex operation at 10 Mbps and 100 Mbps is supported.
Operation mode can be set to auto-negotiation, parallel detection, or manual control. The device is
powered from a single 3.3V power supply.
Applications
■ Combination 10BASE-T/100BASE-TX
Network Interface Cards (NICs)
■ Wireless access points
■ Network printers
Product Features
■ 10/100 Personal Computer Memory Card
International Association (PCMCIA) cards
■ Cable Modems and Set-Top Boxes
■ 3.3V Operation
■ IEEE 802.3-compliant 10BASE-T or
100BASE-TX with integrated filters
■ Auto-negotiation and parallel detection
■ MII interface with extended register
capability
■ Robust baseline wander correction
■ Carrier Sense Multiple Access / Collision
Detection (CSMA/CD) or full-duplex
operation
■ JTAG boundary scan
■ MDIO serial port or hardware pin
configurable
■ Integrated, programmable LED drivers
■ 48-pin Low-profile Quad Flat Package
RESET_L
ADDR[1:0]
MDIO
MDC
TX_EN
TXD[3:0]
TX_CLK
LED/CFG[3:1]
COL
RX_CLK
RXD[3:0]
RX_DV
CRS
RX_ER
Management /
Mode Select
Logic
Register Set
Clock
Generator
Power Supply
Parallel/Serial
Converter
Manchester
Encoder
10
Scrambler 100
& Encoder
Register
Set
Auto
Negotiation
OSP
Pulse
Shaper
+
TP
Driver -
TP Out
JTAG
Collision
Detect
Clock
Generator
Carrier Sense
Data Valid
Error Detect
Serial-to-
Parallel
Converter
Manchester
10 Decoder
100
Decoder &
Descrambler
Media
Select
OSP
Slicer
OSP
Adaptive EQ with
Baseline Wander
Cancellation
+
100TX
-
+
10BT
-
TP In
VCC
GND
REFCLK/XI
XO
TPOP
TPON
TDI
5 TDO
TMS
TCK
TRST_L
TPIP
TPIN
B3387-13
Document Number: 302875-005
Revision Date: 27-Oct-2005
1 page Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver
16 100BASE-TX Transmission with Collision .......................................................... 44
17 Intel® LXT972M Protocol Sublayers.................................................................... 45
18 LED Pulse Stretching ......................................................................................... 54
19 Intel® LXT972M Transceiver Typical Twisted-Pair Interface - Switch ................. 58
20 Intel® LXT972M Transceiver Typical Twisted-Pair Interface - NIC .....................59
21 Intel® LXT972M Transceiver Typical Media Independent Interface .................... 60
22 Intel® LXT972M Transceiver 100BASE-TX Receive Timing ............................... 65
23 Intel® LXT972M Transceiver 100BASE-TX Transmit Timing .............................. 66
24 Intel® LXT972M Transceiver 10BASE-T Receive Timing ................................... 67
25 Intel® LXT972M Transceiver 10BASE-T Transmit Timing .................................. 68
26 Intel® LXT972M Transceiver 10BASE-T Jabber and Unjabber Timing ............... 69
27 Intel® LXT972M Transceiver 10BASE-T SQE (Heartbeat) Timing...................... 70
28 Intel® LXT972M Transceiver Auto-Negotiation and Fast Link Pulse Timing .......71
29 Intel® LXT972M Transceiver Fast Link Pulse Timing .......................................... 71
30 Intel® LXT972M Transceiver MDIO Input Timing ................................................ 72
31 Intel® LXT972M Transceiver MDIO Output Timing .............................................72
32 Intel® LXT972M Transceiver Power-Up Timing .................................................. 73
33 Intel® LXT972M Transceiver RESET_L Pulse Width and Recovery Timing .......74
34 PHY Identifier Bit Mapping ................................................................................. 78
35 Intel® LXT972M Transceiver LQFP Package Specifications............................... 90
36 Sample LQFP Package - Intel® LXT972M Transceiver ...................................... 91
37 Sample Pb-Free (RoHS-Compliant) LQFP Package - Intel® LX972M Transceiver
91
38 Order Matrix for Intel® LXT972M Transceiver ..................................................... 92
Tables
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Related Documents from Intel............................................................................. 10
Intel® LXT972M Transceiver Signal Types ......................................................... 13
Intel® LXT972M Transceiver LQFP Numeric Pin List.......................................... 13
Intel® LXT972M Transceiver MII Data Interface Signal Descriptions.................. 16
Intel® LXT972M Transceiver MII Controller Interface Signal Descriptions .......... 17
Intel® LXT972M Transceiver Network Interface Signal Descriptions .................. 17
Intel® LXT972M Transceiver Standard Bus and Interface Signal Descriptions... 17
Intel® LXT972M Transceiver Configuration and LED Driver Signal Descriptions 18
Intel® LXT972M Transceiver Power, Ground, No-Connect Signal Descriptions . 19
Intel® LXT972M Transceiver JTAG Test Signal Descriptions ............................. 19
Intel® LXT972M Transceiver Pin Types and Modes ........................................... 20
Intel® LXT972M Transceiver - PHY Device Address Selections......................... 26
Hardware Configuration Settings for Intel® LXT972M Transceiver .....................33
Carrier Sense, Loopback, and Collision Conditions ............................................ 39
4B/5B Coding ...................................................................................................... 46
Valid JTAG Instructions....................................................................................... 55
BSR Mode of Operation ...................................................................................... 56
Device ID Register for Intel® LXT972M Transceiver ........................................... 56
Magnetics Requirements.....................................................................................57
I/O Pin Comparison of NIC and Switch RJ-45 Setups ........................................57
Absolute Maximum Ratings for Intel® LXT972M Transceiver ............................. 61
Recommended Operating Conditions for Intel® LXT972M Transceiver ..............61
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
5
5 Page Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver
2.0 Block Diagram for Intel® LXT972M Transceiver
Figure 1 is a block diagram of the LXT972M Transceiver. (This block diagram is the same as the
block diagram on the first page of this document. This copy of the block diagram appears here as a
convenience to the reader.)
Figure 1. Intel® LXT972M Transceiver Block Diagram
RESET_L
ADDR[1:0]
MDIO
MDC
TX_EN
TXD[3:0]
TX_CLK
LED/CFG[3:1]
COL
RX_CLK
RXD[3:0]
RX_DV
CRS
RX_ER
Management /
Mode Select
Logic
Register Set
Clock
Generator
Power Supply
Parallel/Serial
Converter
Manchester
Encoder
10
Scrambler 100
& Encoder
Register
Set
Auto
Negotiation
OSP
Pulse
Shaper
+
TP
Driver -
TP Out
JTAG
Collision
Detect
Clock
Generator
Serial-to-
Parallel
Carrier Sense Converter
Data Valid
Error Detect
Manchester
10 Decoder
100
Decoder &
Descrambler
Media
Select
OSP
Slicer
OSP
Adaptive EQ with
Baseline Wander
Cancellation
+
100TX
-
+
10BT
-
TP In
VCC
GND
REFCLK/XI
XO
TPOP
TPON
TDI
5 TDO
TMS
TCK
TRST_L
TPIP
TPIN
B3387-13
Datasheet
Document Number: 302875-005
Revision Date: 27-Oct-2005
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet LXT972M.PDF ] |
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