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PDF MC33899 Data sheet ( Hoja de datos )
| Número de pieza | MC33899 | |
| Descripción | Programmable H-Bridge Power IC | |
| Fabricantes | Freescale Semiconductor | |
| Logotipo |  |
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Advance Information
Document Number: MC33899
Rev. 2.0, 6/2007
Programmable H-Bridge
Power IC
The 33899 is designed to drive a DC motor in both forward and
reverse shaft rotation under pulse-width modulation (PWM) control of
speed and torque. A current mirror output provides an analog
feedback signal proportional to the load current. A serial peripheral
interface (SPI) is used to select slew rate control, current
compensation limits and to read diagnostic status (faults) of the H-
Bridge drive circuits. SPI diagnostic reporting includes open circuit,
short circuit to VIGNP, short circuit to ground, die temperature range,
and undervoltage on VIGNP.
33899
PROGRAMMABLE H-BRIDGE POWER IC
Features
• Drives Inductive Loads in a Full H-Bridge Configuration
• Current Mirror Output Signal (Gain Selectable via External
Resistor)
VW SUFFIX (Pb-FREE)
98ASH70693A
30-PIN HSOP
• Short Circuit Current Limiting
• Thermal Shutdown (Outputs Latched Off Until Reset via SPI)
• Internal Charge Pump Circuit for the Internal High-Side MOSFETs
ORDERING INFORMATION
• SPI-Selectable Slew Rate Control and Current Limit Control
• Overtemperature Shutdown
Device
Temperature
Range (TA)
Package
• Outputs Can Be Disabled to High-Impedance State
MC33899VW/R2 -40°C to 125°C
30 HSOP
• PWM-able up to 11 kHz @ 3.0 A
• Synchronous Rectification Control of the High-Side MOSFETs
• Low RDS(ON) Outputs at High Junction Temperature (< 165 mΩ @ TA = 125°C, VIGNP = 6.0 V)
• Outputs Survive Shorts to -1.0 V
• Pb-Free Packaging Designated by Suffix Code VW
VDDL +5.0 V VIGNP
MCU
33899
VIGNP
VCC
VDDQ
CSNS
REDIS
CRES
VCCL
FWD
REV
PWM
EN1
EN2
CS
SCLK
D1
D0
LSCMP
GND
S1
S0
RS
Figure 1. 33899 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
1 page  
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ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
ELECTRICAL RATINGS
Protected Power Supply Voltage
Logic Supply Voltage
Logic Output Bias Voltage
VCCL Supply Voltage
Input/Output Voltage (FWD, REV, EN1, EN2, PWM, CS, DI, SCLK, DO, CSNS,
LSCMP, RS, REDIS)
Motor Outputs
Charge Pump Voltage
ESD Voltage (1)
Human Body Model
Machine Model
THERMAL RATINGS
VIGNP
VCC
VDDQ
VCCL
VI / O
VS0, VS1
VCRES
VESD1
VESD2
-0.3 to 40
-0.3 to 7.0
-0.3 to 7.0
-0.3 to 5.0
-0.3 to 7.0
-0.5 to 40
-0.3 to 50
± 2000
± 200
V
V
V
V
V
V
V
V
Operating Temperature(2)
Ambient
Junction
Storage Temperature
Thermal Resistance, Junction to Ambient(3)
TA
TJ
TSTG
RθJA
-40 to 125
-40 to 150
-65 to 150
18
°C
°C
°C/W
Thermal Resistance, Junction to Case (Exposed Pad)
Peak Package Reflow Temperature During Solder Mounting (4)
RθJC
T SOLDER
<0.5
220
°C/W
°C
Notes
1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω), ESD2 testing is performed in
accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
2. The junction temperature is the primary limiting parameter. The module thermal design must provide a low enough thermal impedance
to keep the junction temperature within limits for all anticipated power levels and ambient temperatures.
3. RθJA is referenced to JEDEC standard 2s2p thermal evaluation board at 1W total device power dissipation in still air. Deviations from
this standard will produce corresponding changes in the actual thermal performance.
4. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
Analog Integrated Circuit Device Data
Freescale Semiconductor
33899
5
5 Page 
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TIMING DIAGRAMS
ELECTRICAL CHARACTERISTICS
TIMING DIAGRAMS
CS
t LEAD
t SCLK_HS
SCLK
t DO(ACC)
DO
t SCLK_LS
t DO(VALID)
MSB OUT
DATA
t DI(SU)
t DI(HOLD)
DI MSB IN
DATA
t LAG
t SCLK
t CSN
t DO(HOLD)
t DO(DIS)
LSB OUT
DON’T CARE
tR, tF
LSB IN
5.0V
VENx
Figure 4. SPI Timing Diagram
0.8V
tSODLY
2.0V
tENDLY
VS0-S1
@100mA
Figure 5. Shut Off and Enable Delay
VS0-S1
70%
S0/S1RS
30%
S0/S1RS
70%
30%
Figure 6. Slew Time Measurement
Analog Integrated Circuit Device Data
Freescale Semiconductor
33899
11
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