PDF 89HPES64H16 Data sheet ( Hoja de datos )

Número de pieza	89HPES64H16
Descripción	64-Lane 16-Port PCI Express System Interconnect Switch
Fabricantes	IDT
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No Preview Available ! www.DataSheet4U.com 64-Lane 16-Port PCI Express® System Interconnect Switch ® 89HPES64H16 Data Sheet Device Overview The 89HPES64H16 is a member of the IDT PRECISE™ family of PCI Express® switching solutions. The PES64H16 is a 64-lane, 16-port system interconnect switch optimized for PCI Express packet switching in high-performance applications, supporting multiple simultaneous peer-to-peer traffic flows. Target applications include servers, storage, communications, and embedded systems. Features ◆ High Performance PCI Express Switch – Sixteen maximum switch ports • Eight main ports each of which consists of 8 SerDes • Each x8 main port can further bifurcate to 2 x4-ports – Sixty-four 2.5 Gbps embedded SerDes • Supports pre-emphasis and receive equalization on per-port basis – Delivers 256 Gbps (32 GBps) of aggregate switching capacity – Low-latency cut-through switch architecture – Support for Max Payload Size up to 2048 bytes – Supports two virtual channels and eight traffic classes – PCI Express Base Specification Revision 1.1 compliant ◆ Flexible Architecture with Numerous Configuration Options – Port arbitration schemes utilizing round robin algorithms – Virtual channels arbitration based on priority – Automatic per port link width negotiation to x8, x4, x2 or x1 – Automatic lane reversal on all ports – Automatic polarity inversion on all lanes – Supports locked transactions, allowing use with legacy soft- ware – Ability to load device configuration from serial EEPROM – Ability to control device via SMBus ◆ Highly Integrated Solution – Requires no external components – Incorporates on-chip internal memory for packet buffering and queueing – Integrates sixty-four 2.5 Gbps embedded full duplex SerDes, 8B/10B encoder/decoder (no separate transceivers needed) ◆ Reliability, Availability, and Serviceability (RAS) Features – Redundant upstream port failover capability – Supports optional PCI Express end-to-end CRC checking Block Diagram x8/x4/x2/x1 SerDes DL/Transaction Layer x8/x4/x2/x1 SerDes DL/Transaction Layer x8/x4/x2/x1 SerDes DL/Transaction Layer x8/x4/x2/x1 SerDes DL/Transaction Layer Route Table Frame Buffer 16-Port Switch Core Port Arbitration Scheduler DL/Transaction Layer SerDes DL/Transaction Layer SerDes DL/Transaction Layer SerDes DL/Transaction Layer SerDes x8/x4/x2/x1 x8/x4/x2/x1 x8/x4/x2/x1 x8/x4/x2/x1 64 PCI Express Lanes Up to 8 x8 ports or 16 x4 Ports Figure 1 Internal Block Diagram © 2007 Integrated Device Technology, Inc. IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. 1 of 49 July 19, 2007 1 page IDT 89HPES64H16 Data Sheet Signal PE8RP[3:0] PE8RN[3:0] PE8TP[3:0] PE8TN[3:0] PE9RP[3:0] PE9RN[3:0] PE9TP[3:0] PE9TN[3:0] PE10RP[3:0] PE10RN[3:0] PE10TP[3:0] PE10TN[3:0] PE11RP[3:0] PE11RN[3:0] PE11TP[3:0] PE11TN[3:0] PE12RP[3:0] PE12RN[3:0] PE12TP[3:0] PE12TN[3:0] PE13RP[3:0] PE13RN[3:0] PE13TP[3:0] PE13TN[3:0] PE14RP[3:0] PE14RN[3:0] PE14TP[3:0] PE14TN[3:0] PE15RP[3:0] PE15RN[3:0] PE15TP[3:0] PE15TN[3:0] REFCLKM PEREFCLKP[3:0] PEREFCLKN[3:0] Type Name/Description I PCI Express Port 8 Serial Data Receive. Differential PCI Express receive pairs for port 8. O PCI Express Port 8 Serial Data Transmit. Differential PCI Express transmit pairs for port 8. I PCI Express Port 9 Serial Data Receive. Differential PCI Express receive pairs for port 9. When port 8 is merged with port 9, these signals become port 8 receive pairs for lanes 4 through 7. O PCI Express Port 9 Serial Data Transmit. Differential PCI Express transmit pairs for port 9. When port 8 is merged with port 9, these signals become port 8 transmit pairs for lanes 4 through 7. I PCI Express Port 10 Serial Data Receive. Differential PCI Express receive pairs for port 10. O PCI Express Port 10 Serial Data Transmit. Differential PCI Express transmit pairs for port 10. I PCI Express Port 11 Serial Data Receive. Differential PCI Express receive pairs for port 11. When port 10 is merged with port 11, these signals become port 10 receive pairs for lanes 4 through 7. O PCI Express Port 11 Serial Data Transmit. Differential PCI Express transmit pairs for port 11. When port 10 is merged with port 11, these signals become port 10 trans- mit pairs for lanes 4 through 7. I PCI Express Port 12 Serial Data Receive. Differential PCI Express receive pairs for port 12. O PCI Express Port 12 Serial Data Transmit. Differential PCI Express transmit pairs for port 12. I PCI Express Port 13 Serial Data Receive. Differential PCI Express receive pairs for port 13. When port 12 is merged with port 13, these signals become port 12 receive pairs for lanes 4 through 7. O PCI Express Port 13 Serial Data Transmit. Differential PCI Express transmit pairs for port 13. When port 12 is merged with port 13, these signals become port 12 trans- mit pairs for lanes 4 through 7. I PCI Express Port 14 Serial Data Receive. Differential PCI Express receive pairs for port 14. O PCI Express Port 14 Serial Data Transmit. Differential PCI Express transmit pairs for port 14. I PCI Express Port 15 Serial Data Receive. Differential PCI Express receive pairs for port 15. When port 14 is merged with port 15, these signals become port 14 receive pairs for lanes 4 through 7. O PCI Express Port 15 Serial Data Transmit. Differential PCI Express transmit pairs for port 15. When port 14 is merged with port 15, these signals become port 14 trans- mit pairs for lanes 4 through 7. I PCI Express Reference Clock Mode Select. This signal selects the frequency of the reference clock input. 0x0 - 100 MHz 0x1 - 125 MHz I PCI Express Reference Clock. Differential reference clock pair input. This clock is used as the reference clock by on-chip PLLs to generate the clocks required for the system logic and on-chip SerDes. The frequency of the differential reference clock is determined by the REFCLKM signal. Table 2 PCI Express Interface Pins (Part 2 of 2) 5 of 49 July 19, 2007 5 Page IDT 89HPES64H16 Data Sheet Signal VDDAPE VSS VTTPE Type Name/Description I PCI Express Analog Power. PCI Express analog power used by the PLL and bias generator. I Ground. PCI Express Serial Data Transmit Termination Voltage. This pin allows the driver termination voltage to be set, enabling the system designer to control the Common Mode Voltage and output voltage swing of the corresponding PCI Serial Data Transmit differential pair. Table 7 Power and Ground Pins 11 of 49 July 19, 2007 11 Page

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