Datasheet.kr   

89HPES8T5A 데이터시트 PDF




IDT에서 제조한 전자 부품 89HPES8T5A은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 89HPES8T5A 자료 제공

부품번호 89HPES8T5A 기능
기능 8-Lane 5-Port PCI Express Switch
제조업체 IDT
로고 IDT 로고


89HPES8T5A 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 29 페이지수

미리보기를 사용할 수 없습니다

89HPES8T5A 데이터시트, 핀배열, 회로
www.DataSheet4U.com
8-Lane 5-Port
PCI Express® Switch
®
89HPES8T5A
Data Sheet
Advance Information*
Device Overview
The 89HPES8T5A is a member of IDT’s PRECISE™ family of PCI
Express switching solutions. The PES8T5A is an 8-lane, 5-port periph-
eral chip that performs PCI Express Base switching. It provides connec-
tivity and switching functions between a PCI Express upstream port and
up to four downstream ports and supports switching between down-
stream ports.
Features
High Performance PCI Express Switch
– Eight 2.5Gbps PCI Express lanes
– Five switch ports
– Upstream port is x4
– Downstream ports are x1
– Low-latency cut-through switch architecture
– Support for Max Payload Sizes up to 256 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
Flexible Architecture with Numerous Configuration Options
– Automatic lane reversal on all ports
– Automatic polarity inversion on all lanes
– Ability to load device configuration from serial EEPROM
Legacy Support
– PCI compatible INTx emulation
– Bus locking
Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering and
queueing
– Integrates eight 2.5 Gbps embedded SerDes with 8B/10B
encoder/decoder (no separate transceivers needed)
Reliability, Availability, and Serviceability (RAS) Features
– Internal end-to-end parity protection on all TLPs ensures data
integrity even in systems that do not implement end-to-end
CRC (ECRC)
– Supports ECRC and Advanced Error Reporting
– Supports PCI Express Native Hot-Plug, Hot-Swap capable I/O
– Compatible with Hot-Plug I/O expanders used on PC mother-
boards
Power Management
– Utilizes advanced low-power design techniques to achieve low
typical power consumption
– Supports PCI Power Management Interface specification (PCI-
PM 1.2)
– Unused SerDes are disabled.
– Supports Advanced Configuration and Power Interface Speci-
fication, Revision 2.0 (ACPI) supporting active link state
Testability and Debug Features
– Built in Pseudo-Random Bit Stream (PRBS) generator
– Numerous SerDes test modes
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
Block Diagram
Frame Buffer
5-Port Switch Core / 8 PCI Express Lanes
Route Table
Port
Arbitration
Scheduler
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
Transaction Layer
Data Link Layer
Mux / Demux
Phy
Logical
Layer
SerDes
(Port 0)
(Port 2)
(Port 3)
(Port 4)
Figure 1 Internal Block Diagram
© 2007 Integrated Device Technology, Inc.
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
1 of 29
*Notice: The information in this document is subject to change without notice
(Port 5)
September 7, 2007




89HPES8T5A pdf, 반도체, 판매, 대치품
IDT 89HPES8T5A Data Sheet
General Purpose Input/Output
The PES8T5A provides 11 General Purpose Input/Output (GPIO) pins that may be used by the system designer as bit I/O ports. Each GPIO pin
may be configured independently as an input or output through software control. Some GPIO pins are shared with other on-chip functions. These
alternate functions may be enabled via software, SMBus slave interface, or serial configuration EEPROM.
Pin Description
The following tables lists the functions of the pins provided on the PES8T5A. Some of the functions listed may be multiplexed onto the same pin.
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.
Signal
PE0RP[3:0]
PE0RN[3:0]
PE0TP[3:0]
PE0TN[3:0]
PE2RP[0]
PE2RN[0]
PE2TP[0]
PE2TN[0]
PE3RP[0]
PE3RN[0]
PE3TP[0]
PE3TN[0]
PE4RP[0]
PE4RN[0]
PE4TP[0]
PE4TN[0]
PE5RP[0]
PE5RN[0]
PE5TP[0]
PE5TN[0]
PEREFCLKP
PEREFCLKN
REFCLKM
Type
Name/Description
I PCI Express Port 0 Serial Data Receive. Differential PCI Express receive
pairs for port 0.
O PCI Express Port 0 Serial Data Transmit. Differential PCI Express trans-
mit pairs for port 0.
I PCI Express Port 2 Serial Data Receive. Differential PCI Express receive
pair for port 2.
O PCI Express Port 2 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 2.
I PCI Express Port 3 Serial Data Receive. Differential PCI Express receive
pair for port 3.
O PCI Express Port 3 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 3.
I PCI Express Port 4 Serial Data Receive. Differential PCI Express receive
pair for port 4.
O PCI Express Port 4 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 4.
I PCI Express Port 5 Serial Data Receive. Differential PCI Express receive
pair for port 5.
O PCI Express Port 5 Serial Data Transmit. Differential PCI Express trans-
mit pair for port 5.
I PCI Express Reference Clock. Differential reference clock pair input. This
clock is used as the reference clock by on-chip PLLs to generate the clocks
required for the system logic and on-chip SerDes. The frequency of the dif-
ferential reference clock is determined by the REFCLKM signal.
I PCI Express Reference Clock Mode Select. This signal selects the fre-
quency of the reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
Table 2 PCI Express Interface Pins
4 of 29
September 7, 2007

4페이지










89HPES8T5A 전자부품, 판매, 대치품
IDT 89HPES8T5A Data Sheet
Signal
RSTHALT
SWMODE[2:0]
WAKEN
Type
Name/Description
I Reset Halt. When this signal is asserted during a PCI Express fundamental
reset, the PES8T5A executes the reset procedure and remains in a reset
state with the Master and Slave SMBuses active. This allows software to
read and write registers internal to the device before normal device opera-
tion begins. The device exits the reset state when the RSTHALT bit is
cleared in the PA_SWCTL register by an SMBus master.
I Switch Mode. These configuration pins determine the PES8T5A switch
operating mode.
0x0 - Normal switch mode
0x1 - Normal switch mode with Serial EEPROM initialization
0x2 - through 0xF Reserved
I/O Wake Input/Output. The WAKEN signal is an input or output. The WAKEN
signal input/output selection can be made through the WAKEDIR bit setting
in the WAKEUPCNTL register.
Table 5 System Pins (Part 2 of 2)
Signal
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
Type
Name/Description
I JTAG Clock. This is an input test clock used to clock the shifting of data
into or out of the boundary scan logic or JTAG Controller. JTAG_TCK is
independent of the system clock with a nominal 50% duty cycle.
I JTAG Data Input. This is the serial data input to the boundary scan logic or
JTAG Controller.
O JTAG Data Output. This is the serial data shifted out from the boundary
scan logic or JTAG Controller. When no data is being shifted out, this signal
is tri-stated.
I JTAG Mode. The value on this signal controls the test mode select of the
boundary scan logic or JTAG Controller.
I JTAG Reset. This active low signal asynchronously resets the boundary
scan logic and JTAG TAP Controller. An external pull-up on the board is
recommended to meet the JTAG specification in cases where the tester
can access this signal. However, for systems running in functional mode,
one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
Table 6 Test Pins
Signal
VDDCORE
VDDIO
VDDPE
VDDAPE
VTTPE
VSS
Type
Name/Description
I Core VDD. Power supply for core logic.
I I/O VDD. LVTTL I/O buffer power supply.
I PCI Express Digital Power. PCI Express digital power used by the digital
power of the SerDes.
I PCI Express Analog Power. PCI Express analog power used by the PLL
and bias generator.
I PCI Express Termination Power.
I Ground.
Table 7 Power and Ground Pins
7 of 29
September 7, 2007

7페이지


구       성 총 29 페이지수
다운로드[ 89HPES8T5A.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
89HPES8T5A

8-Lane 5-Port PCI Express Switch

IDT
IDT

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵