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PDF CS4382 Data sheet ( Hoja de datos )
| Número de pieza | CS4382 | |
| Descripción | 192 kHz 8-Channel D/A Converter | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS4382
114 dB, 192 kHz 8-Channel D/A Converter
Features
z 24-bit Conversion
z Up to 192 kHz Sample Rates
z 114 dB Dynamic Range
z -100 dB THD+N
z Supports PCM and DSD Data Formats
z Selectable Digital Filters
z Volume Control with Soft Ramp
– 1 dB Step Size
– Zero Crossing Click-free Transitions
z Dedicated DSD inputs
z Low Clock Jitter Sensitivity
z Simultaneous Support for Two Synchronous
Sample Rates for DVD Audio
z µC or Stand-alone Operation
I
Description
The CS4382 is a complete 8-channel digital-to-analog
system including digital interpolation, fifth-order delta-
sigma digital-to-analog conversion, digital de-emphasis,
volume control and analog filtering. The advantages of
this architecture include: ideal differential linearity, no
distortion mechanisms due to resistor matching errors,
no linearity drift over time and temperature and a high
tolerance to clock jitter.
The CS4382 accepts PCM data at sample rates from
4 kHz to 192 kHz, DSD audio data, and operates over a
wide power supply range. These features are ideal for
multi-channel audio systems including DVD players,
SACD players, A/V receivers, digital TV’s, mixing con-
soles, effects processors, and automotive audio
systems.
ORDERING INFORMATION
CS4382-KQZ, Lead Free -10 to 70 °C 48-pin LQFP
CDB4382
Evaluation Board
RST
VLS
S C LK1
LRC K1
SCLK 2
L RCK2
SD I N1
SD I N2
SD I N3
SD I N4
D S D _S C LK(M 3)
M CLK
÷2
8
DSDxx
S C L/C C LK (M 1) S D A /C D IN (M 2) A D 0/C S (M 0) V LC
C ontrol P ort(S tand-A lone M ode S elect)
V olu m e C o ntro l
M ixer
V olu m e C o ntro l
V olu m e C o ntro l
M ixer
V olu m e C ontro l
V olu m e C o ntro l
M ixer
V olu m e C ontro l
V olu m e C o ntro l
M ixer
V olu m e C ontro l
I n t e r p o la t i o n F ilt e r
I n t e r p o la t i o n F i lt e r
I n t e r p o la t i o n F i lt e r
I n t e r p o la ti o n F ilt e r
I n t e r p o la t i o n F i lt e r
I n t e r p o la ti o n F ilt e r
I n t e r p o la t i o n F i lt e r
I n t e r p o la ti o n F ilt e r
MUTEC1
M U TE C234
E xte rnal
M ute C o ntrol
∆Σ D A C
A n a lo g F ilte r
∆Σ D A C
∆Σ D A C
A n a lo g F ilte r
A n a lo g F ilte r
∆Σ D A C
∆Σ D A C
A n a lo g F ilte r
A n a lo g F ilte r
∆Σ D A C
∆Σ D A C
∆Σ D A C
A n a lo g F ilte r
A n a lo g F ilte r
A n a lo g F ilte r
VD
GND
GND
VA
A O U T A1+
A O U T A1-
A O U T B1+
A O U T B1-
A O U T A2+
A O U T A2-
A O U T B2+
A O U T B2-
A O U T A3+
A O U T A3-
A O U T B3+
A O U T B3-
A O U T A4+
A O U T A4-
A O U T B4+
A O U T B4-
VQ
F ILT +
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2004
(All Rights Reserved)
NOV ‘04
DS514F1
1 page  
CS4382
ANALOG CHARACTERISTICS (Continued)
Parameters
Analog Output - All PCM modes and DSD
Full Scale Differential Output Voltage (Note 4)
Quiescent Voltage
Max Current from VQ
Interchannel Gain Mismatch
Gain Drift
Output Impedance
(Note 4)
AC-Load Resistance
Load Capacitance
Symbol
VFS
VQ
IQMAX
ZOUT
RL
CL
Min
86% VA
-
-
-
-
-
3
-
Typ
91% VA
50% VA
1
0.1
100
100
-
-
Max
96% VA
-
-
-
-
-
-
100
Units
Vpp
VDC
µA
dB
ppm/°C
Ω
kΩ
pF
POWER AND THERMAL CHARACTERISTICS
Parameters
Symbol Min Typ Max Units
Power Supplies
Power Supply Current
normal operation, VA= 5 V
(Note 5)
VD= 5 V
VD= 3.3 V
Interface current, VLC=5 V (Note 6, 7)
VLS=5 V
power-down state (all supplies) (Note 8)
IA
ID
ID
ILC
ILS
Ipd
- 60 66 mA
- 45 70 mA
- 30 46 mA
- 2 - µA
- 84 -
µA
- 200 -
µA
Power Dissipation
VA = 5 V, VD = 3.3 V
VA = 5 V, VD = 5 V
(Note 5)
normal operation
power-down (Note 8)
normal operation
power-down (Note 8)
-
400 485
mW
- 1 - mW
-
525 680
mW
- 1 - mW
Package Thermal Resistance
Power Supply Rejection Ratio (Note 9)
θJA - 48 - °C/Watt
θJC - 15 - °C/Watt
(1 kHz) PSRR
-
60
-
dB
(60 Hz)
- 40 -
dB
Notes: 4. VFS is tested under load RL and includes attenuation due to ZOUT
5. Current consumption increases with increasing FS within a given speed mode and is signal dependant.
Max values are based on highest FS and highest MCLK.
6. ILC measured with no external loading on the SDA pin.
7. This specification is violated when the VLC supply is greater than VD and when pin 16 (M1/SDA) is tied
or pulled low. Logic tied to pin 16 needs to be able to sink this current.
8. Power down mode is defined as RST pin = Low with all clock and data lines held static.
9. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 5 and 6.
DS514F1
5
5 Page 
CS4382
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT
(For KQZ TA = -10 to +70 °C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, CL = 30 pF)
Parameter
Symbol
Min
Max
CCLK Clock Frequency
fsclk - M------C-----L----K--
2
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
(Note 22)
tsrs
tspi
tcsh
tcss
tscl
500
500
1.0
20
--------1---------
MCLK
-
-
-
-
-
CCLK High Time
tsch --------1---------
MCLK
-
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
(Note 23)
(Note 24)
(Note 24)
tdsu
tdh
tr2
tf2
40
15
-
-
-
-
100
100
Unit
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
Notes: 22. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
23. Data must be held for sufficient time to bridge the transition time of CCLK.
24. For FSCK < 1 MHz.
RST t srs
CS
CCLK
C D IN
t spi t css
t r2
t scl t sch
t f2
t dsu t dh
Figure 4. Control Port Timing - SPI Format
t csh
DS514F1
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS4382.PDF ] | |
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