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ICSSSTUAF32866B 데이터시트 PDF




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부품번호 ICSSSTUAF32866B 기능
기능 25-BIT CONFIGURABLE REGISTERED BUFFER
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ICSSSTUAF32866B 데이터시트, 핀배열, 회로
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DATASHEET
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 CONFIDENTIAL IDT74SSTUBF32866B
Description
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is
designed for 1.7-V to 1.9-V VDD operation.
All clock and data inputs are compatible with the JEDEC
standard for SSTL_18. The control inputs are LVCMOS. All
outputs are 1.8-V CMOS drivers that have been optimized
to drive the DDR-II DIMM load. IDT74SSTUBF32866B
operates from a differential clock (CLK and CLK). Data are
registered at the crossing of CLK going high, and CLK
going low.
The C0 input controls the pinout configuration of the 1:2
pinout from A configuration (when low) to B configuration
(when high). The C1 input controls the pinout configuration
from 25-bit 1:1 (when low) to 14-bit 1:2 (when high).
A - Pair Configuration (C01 = 0, C11 = 1 and C02 = 0,
C12 = 1)
Parity that arrives one cycle after the data input to which it
applies is checked on the PAR_IN of the first register. The
second register produces to PPO and QERR signals. The
QERR of the first register is left floating. The valid error
information is latched on the QERR output of the second
register. If an error occurs QERR is latched low for two
cycles or until RESET is low.
B - Single Configuration (C0 = 0, C1 = 0)
The device supports low-power standby operation. When
the RESET input (RESET) is low, the differential input
receivers are disabled, and undriven (floating) data, clock
and reference voltage (VREF) inputs are allowed. In
addition, when RESET is low all registers are reset, and all
outputs are forced low. The LVCMOS RESET and Cn inputs
must always be held at a valid logic high or low level. To
ensure defined outputs from the register before a stable
clock has been supplied, RESET must be held in the low
state during power up.
In the DDR-II RDIMM application, RESET is specified to be
completely asynchronous with respect to CLK and CLK.
Therefore, no timing relationship can be guaranteed
between the two. When entering reset, the register will be
cleared and the outputs will be driven low quickly, relative to
the time to disable the differential input receivers. However,
when coming out of reset, the register will become active
quickly, relative to the time to enable the differential input
receivers. As long as the data inputs are low, and the clock
is stable during the time from the low-to-high transition of
RESET until the input receivers are fully enabled, the
design of the IDT74SSTUBF32866B must ensure that the
outputs will remain low, thus ensuring no glitches on the
output.
The device monitors both DCS and CSR inputs and will
gate the Qn outputs from changing states when both DCS
and CSR inputs are high. If either DCS and CSR input is
low, the Qn outputs will function normally. The RESET input
has priority over the DCS and CSR control and will force the
outputs low. If the DCS-control functionality is not desired,
then the CSR input can be hardwired to ground, in which
case, the setup-time requirement for DCS would be the
same as for the other D data inputs. Package options
include 96-ball LFBGA (MO-205CC).
Features
25-bit 1:1 or 14-bit 1:2 registered buffer with parity check
functionality
Supports SSTL_18 JEDEC specification on data inputs
and outputs
Supports LVCMOS switching levels on C0, C1, and
RESET inputs
Low voltage operation: VDD = 1.7V to 1.9V
Available in 96-ball LFBGA package
Applications
DDR2 Memory Modules
Provides complete DDR DIMM solution with
ICS98ULPA877A or IDTCSPUA877A
Ideal for DDR2 667 and 800
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
1
CONFIDENTIAL
IDT74SSTUBF32866B
7067/9




ICSSSTUAF32866B pdf, 반도체, 판매, 대치품
IDT74SSTUBF32866B
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Pin Configurations
14 BIT 1:2 REGISTERS
1 2 3 45 6
A DCKE PPO VREF VDD QCKEA QCKEB
B D2
NC GND GND Q2A Q2B
C D3
NC VDD VDD Q3A Q3B
D DODT QERR GND GND QODTA QODTB
E D5 NC VDD
F D6
NC GND
G PAR_IN RESET VDD
VDD
GND
VDD
Q5A
Q6A
C1
Q5B
Q6B
C0
H CLK
J CLK
K D8
DCS
CSR
NC
GND
VDD
GND
GND QCSA QCSB
VDD
ZOH
ZOL
GND Q8A Q8B
L D9
NC VDD VDD Q9A Q9B
M D10 NC GND GND Q10A Q10B
N D11 NC
VDD VDD Q11A Q11B
P D12 NC GND GND Q12A Q12B
R D13 NC
VDD VDD Q13A Q13B
T D14 NC VREF VDD Q14A Q14B
REGISTER A (C0 = 0, C1 = 1)
25 BIT 1:1 REGISTER
1 234 56
A DCKE PPO VREF
B D2 D15 GND
C D3 D16 VDD
D DODT QERR GND
E D5 D17 VDD
F D6 D18 GND
G PAR_IN RESET VDD
H CLK DCS GND
J CLK CSR VDD
K D8 D19 GND
L D9 D20 VDD
VDD QCKE
GND Q2
VDD Q3
GND QODT
VDD Q5
GND Q6
VDD C1
GND QCS
VDD
ZOH
GND Q8
VDD Q9
NC
Q15
Q16
NC
Q17
Q18
C0
NC
ZOL
Q19
Q20
M D10 D21 GND GND Q10 Q21
N D11
P D12
D22
D23
VDD
GND
VDD
GND
Q11
Q12
Q22
Q23
R D13 D24
VDD VDD Q13 Q24
T D14 D25 VREF VDD Q14 Q25
C0 = 0, C1 = 0
COMMERCIAL TEMPERATURE GRADE
1 23 4 5 6
A D1
PPO VREF VDD Q1A Q1B
B D2
NC GND GND Q2A Q2B
C D3
NC VDD VDD Q3A Q3B
D D4 QERR GND GND Q4A Q4B
E D5
NC VDD VDD Q5A Q5B
F D6
NC GND GND Q6A Q6B
G PAR_IN RESET VDD VDD C1
C0
H CLK DCS GND GND QCSA QCSB
J CLK CSR VDD VDD ZOH ZOL
K D8
NC GND GND Q8A Q8B
L D9
NC VDD VDD Q9A Q9B
M D10 NC GND GND Q10A Q10B
N DODT NC
VDD VDD QODTA QODTB
P D12
NC GND GND Q12A Q12B
R D13 NC VDD VDD Q13A Q13B
T DCKE NC VREF VDD QCKEA QCKEB
REGISTER B (C0 = 1, C1 = 1)
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
4
CONFIDENTIAL
IDT74SSTUBF32866B
7067/9

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ICSSSTUAF32866B 전자부품, 판매, 대치품
IDT74SSTUBF32866B
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
Parity and Standby Function Table
RESET DCS CSR
Inputs1
CLK CLK
Σ of Inputs = H
(D1 - D25)
PAR_IN2
Outputs
PPO
QERR3
H LX ↑ ↓
Even
L LH
H LX ↑ ↓
Odd
L HL
H LX ↑ ↓
Even
H HL
H LX ↑ ↓
Odd
H LH
H XL
↑↓
Even
L LH
H XL
↑↓
Odd
L HL
H XL
↑↓
Even
H HL
H XL
↑↓
Odd
H LH
H HH ↑ ↓
X
X PPO0
H X X L or H L or H
X
X PPO0
L X or X or X or X or X or Floating X or Floating
Floating Floating Floating Floating
L
QERR0
QERR0
H
1 H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
= LOW to HIGH
= HIGH to LOW
Data Inputs = D2, D3, D5, D6, D8 - D25 when C0 = 0 and C1 = 0.
Data Inputs = D2, D3, D5, D6, D8 - D14 when C0 = 0 and C1 = 1.
Data Inputs = D1 - D6, D8 - D10, D12, D13 when C0 = 1 and C1 = 1.
2 PAR_IN arrives one clock cycle after the data to which it applies when C0 = 0, and two clock cycles when
C0 = 1.
3 This transition assumes QERR is HIGH at the crossing of CLK going HIGH and CLK going LOW. If
QERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW.
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
7
CONFIDENTIAL
IDT74SSTUBF32866B
7067/9

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