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ICSSSTUAF32868B 데이터시트 PDF




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부품번호 ICSSSTUAF32868B 기능
기능 28-BIT CONFIGURABLE REGISTERED BUFFER
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ICSSSTUAF32868B 데이터시트, 핀배열, 회로
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DATASHEET
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
ICSSSTUAF32868B
Description
This 28-bit 1:2 configurable registered buffer is designed for
1.7V to 1.9V VDD operation. All inputs are compatible with
the JEDEC standard for SSTL_18, except the chip-select
gate-enable (CSGEN), control (C), and reset (RESET)
inputs, which are LVCMOS. All outputs are edge-controlled
circuits optimized for unterminated DIMM loads, and meet
SSTL_18 specifications, except the open-drain error
(QERR) output.
The ICSSSTUAF32868B operates from a differential clock
(CLK and CLK). Data are registered at the crossing of CLK
going high and CLK going low. The device supports
low-power standby operation. When RESET is low, the
differential input receivers are disabled, and undriven
(floating) data, clock, and reference voltage (Vref) inputs
are allowed. In addition, when RESET is low, all registers
are reset and all outputs are forced low except QERR. The
LVCMOS RESET and C inputs must always be held at a
valid logic high or low level. To ensure defined outputs from
the register before a stable clock has been supplied,
RESET must be held in the low state during power up. In
the DDR2 RDIMM application, RESET is specified to be
completely asynchronous with respect to CLK and CLK.
Therefore, no timing relationship can be ensured between
the two. When entering reset, the register will be cleared
and the data outputs will be driven low quickly, relative to
the time to disable the differential input receivers. However,
when coming out of reset, the register will become active
quickly, relative to the time to enable the differential input
receivers. As long as the data inputs are low, and the clock
is stable during the time from the low-to-high transition of
RESET until the input receivers are fully enabled, the
design of the ICSSSTUAF32868B must ensure that the
outputs will remain low, thus ensuring no glitches on the
output.
The ICSSSTUAF32868B includes a parity checking
function. Parity, which arrives one cycle after the data input
to which it applies, is checked on the PAR_IN input of the
device. The corresponding QERR output signal for the data
inputs is generated two clock cycles after the data, to which
the QERR signal applies, is registered. The
ICSSSTUAF32868B accepts a parity bit from the memory
controller on the parity bit (PAR_IN) input, compares it with
the data received on the DIMM-independent D-inputs
(D1-D5, D7, D9-D12, D17-D28 when C = 0; or D1-D12,
D17-D20, D22, D24-D28 when C = 1) and indicates
whether a parity error has occurred on the open-drain
QERR pin (active low). The convention is even parity, i.e.,
valid parity is defined as an even number of ones across the
DIMM-independent data inputs combined with the parity
input bit. To calculate parity, all DIMM-independent D-inputs
must be tied to a known logic state. If an error occurs and
the QERR output is driven low, it stays latched low for a
minimum of two clock cycles or until RESET is driven low. If
two or more consecutive parity errors occur, the QERR
output is driven low and latched low for a clock duration
equal to the parity error duration or until RESET is driven
low. If a parity error occurs on the clock cycle before the
device enters the low-power (LPM) and the QERR output is
driven low, then it stays lateched low for the LPM duration
plus two clock cycles or until RESET is driven low. The
DIMM-dependent signals (DCKE0, DCKE1, DODT0,
DODT1, DCS0 and DCS1) are not included in the parity
check computation.
The C input controls the pinout configuration from
register-A configuration (when low) to register-B
configuration (when high). The C input should not be
switched during normal operation. It should be hardwired to
a valid low or high level to configure the register in the
desired mode. The device also supports low-power active
operation by monitoring both system chip select (DCS0 and
DCS1) and CSGEN inputs and will gate the Qn outputs
from changing states when CSGEN, DCS0, and DCS1
inputs are high. If CSGEN, DCS0 orDCS1 input is low, the
Qn outputs will function normally. Also, if both DCS0 and
DCS1 inputs are high, the device will gate the QERR output
from changing states. If either DCS0 orDCS1 is low, the
QERR output will function normally. The RESET input has
priority over the DCS0 and DCS1 control and when driven
low will force the Qn outputs low, and the QERR output
high. If the chip-select control functionality is not desired,
then the CSGEN input can be hard-wired to ground, in
which case, the setup-time requirement for DCS0 and
DCS1 would be the same as for the other D data inputs. To
control the low-power mode with DCS0 and DCS1 only,
then the CSGEN input should be pulled up to Vdd through a
pullup resistor. The two VREF pins (A1 and V1) are
connected together internally by approximately 150.
However, it is necessary to connect only one of the two
VREF pins to the external VREF power supply. An unused
VREF pin should be terminated with a VREF coupling
capacitor.
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
1
ICSSSTUAF32868B
7102/2




ICSSSTUAF32868B pdf, 반도체, 판매, 대치품
ICSSSTUAF32868B
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Block Diagram
M2
RESET
CLK
CLK
L1
M1
VREF A5, AB5
DCKE0, W1, Y1
DCKE1
2
2
DODT0, K1, J1
DODT1
2
2
DCS0
N1
CSGEN L2
DCS1
P1
D1 A2
COMMERCIAL TEMPERATURE GRADE
D
CK
R
Q
2
D
CK
R
Q
2
D
CK
R
Q
U2, V2 QCKE0A,
QCKE1A
R8, U8 QCKE0B,
QCKE1B
K2, J2 QODT0A,
QODT1A
L7, L8 QODT0B,
QODT1B
N2 QCS0A
M7 QCS0B
D
CK
R
Q
One of 22 Channels
D CE
CK Q
R
P2 QCS1A
M8 QCS1B
A7
Q1A
A8
Q1B
TO 21 OTHER CHANNELS
(D2-D12, D17-D20, D22, D24-D28)
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
4
ICSSSTUAF32868B
7102/2

4페이지










ICSSSTUAF32868B 전자부품, 판매, 대치품
ICSSSTUAF32868B
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
COMMERCIAL TEMPERATURE GRADE
Pin Configuration
A D2
D1
C
B D4
D3
C
D6
(DCKE1)
D5
D
D8
(DCKE0)
D7
E
D9
Q6A
(QCKE1A)
F
D10
Q8A
(QCKE0A)
G D11
Q10A
H D12
Q12A
VDD
GND
VDD
GND
VDD
GND
VDD
J DCS1
QCS1
GND
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
K DCS0
QCS0
VDD
L CLK CSGEN PAR_IN
M
CLK
RESET
QERR
N
D15 Q15A
(DODT0) (QODT0A)
P
D16 Q16A
(DODT1) (QODT1A)
R D17
Q17A
GND
VDD
GND
T D18
Q19A
VDD
U D19
V D20
Q21A
Q23A
GND
VDD
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
W D21
D22
GND
GND
Y D23
D24
VDD
VDD
AA D24
D26
GND
GND
AB D27
D28
NC VDD
1 2 34
VREF
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VREF
5
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
Q1A
Q1B
Q2A
Q3A
Q2B
Q3B
Q4A
Q4B
Q5A
Q7A
Q9A
Q11A
Q10B
Q5B
Q6B
(QCKE0B)
Q7B
Q8B
(QCKE0B)
Q9B
VDD
GND
VDD
Q12B
Q11B
Q14B
(QCS0B)
Q15B
(QODT0B)
Q13B
(QCS1B)
Q16B
(QODT1B)
GND
Q17B
Q18B
VDD
GND
VDD
GND
VDD
Q19B
Q18A
Q20A
Q22A
Q24A
Q20B
Q21B
Q22B
Q23B
Q24B
GND
VDD
GND
VDD
6
Q25A
Q26A
Q27A
Q28A
7
Q25B
Q26B
Q27B
Q28B
8
A D2
B D4
C D6
D D8
E D9
F D10
D1
D3
D5
D7
Q6A
Q8A
C
VDD
GND
VDD
GND
VDD
G D11
Q10A
GND
H D12
Q12A
D13 Q13A
J (DODT1) (QODT1A)
D14 Q14A
K (DODT0) (QODT0A)
VDD
GND
VDD
L CLK CSGEN PAR_IN
M CLK RESET
N
D15
(DCS0)
Q15A
(QCS0A)
D16 Q16A
P (DCS1) (QCS1A)
QERR
GND
VDD
R D17
Q17A
GND
T D18
Q19A
Q21A
U D19 (QCKE0A)
V D20
Q23A
(QCKE1A)
D21
W (DCKE0)
D22
D23
Y (DCKE1)
D24
AA D25
AB D27
1
D26
D28
2
VDD
GND
VDD
GND
VDD
GND
NC
3
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
4
VREF
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VREF
5
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
Q1A
Q2A
Q3A
Q4A
Q5A
Q7A
Q9A
Q11A
Q10B
Q1B
Q2B
Q3B
Q4B
Q5B
Q6B
Q7B
Q8B
Q9B
VDD
GND
VDD
Q12B
Q11B
Q14B
(QODT0B)
Q15B
(QCS0B)
Q13B
(QODT1B)
Q16B
(QCS1B)
GND
Q17B
Q18B
VDD
GND
VDD
GND
VDD
Q19B
Q18A
Q20A
Q22A
Q24A
Q20B
Q21B
(QCKE0B)
Q22B
Q23B
(QCKE1B)
Q24B
GND
VDD
GND
VDD
6
Q25A
Q26A
Q27A
Q28A
7
Q25B
Q26B
Q27B
Q28B
8
1:2 REGISTER A (C = 0)
NOTE: NC denotes a no-connect (ball present but not
connected to the die).
1:2 REGISTER B (C = 1)
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
7
ICSSSTUAF32868B
7102/2

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