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부품번호 S2042 기능
기능 (S2042 / S2043) HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
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S2042 데이터시트, 핀배열, 회로
www.DataSheet4U.com
PRELIMINARY
DHEIVGICHEPSEPERCFIOFIRCAMTAIONNCE SERIAL INTERFACE CIRCUITS
BHiICGMHOPSERPFEOCRLMCALNOCCEK SGEERNIAERLAINTTOERRFACE CIRCUITS
®
S2042/S2043
S2042/S2043
FEATURES
• Functionally compliant with ANSI X3T11 Fibre
Channel physical and transmission protocol
standards
• S2042 transmitter incorporates phase-locked loop
(PLL) providing clock synthesis from low-speed
reference
• S2043 receiver PLL configured for clock and
data recovery
• 1062, 531 and 266 Mb/s operation
• 10- or 20-bit parallel TTL compatible interface
• 1 watt typical power dissipation for chipset
• +3.3/+5V power supply
• Low-jitter serial PECL compatible interface
• Lock detect
• Local loopback
• 10mm x 10mm 52 PQFP package
• Fibre Channel framing performed by receiver
• Continuous downstream clocking from receiver
• TTL compatible outputs possible with +5V I/O
power supply
APPLICATIONS
High-speed data communications
• Supercomputer/Mainframe
• Workstation
• Switched networks
• Proprietary extended backplanes
• Mass storage devices/RAID drives
GENERAL DESCRIPTION
The S2042 and S2043 transmitter and receiver pair
are designed to perform high-speed serial data trans-
mission over fiber optic or coaxial cable interfaces
conforming to the requirements of the ANSI X3T11
Fibre Channel specification. The chipset is select-
able to 1062, 531 or 266 Mbit/s data rates with
associated 10- or 20-bit data word.
The chipset performs parallel-to-serial and serial-to-
parallel conversion and framing for block-encoded
data. The S2042 on-chip PLL synthesizes the high-
speed clock from a low-speed reference. The S2043
on-chip PLL synchronizes directly to incoming digital
signals to receive the data stream. The transmitter
and receiver each support differential PECL-compat-
ible I/O for fiber optic component interfaces, to
minimize crosstalk and maximize data integrity. Lo-
cal loopback allows for system diagnostics. The TTL
I/O section can operate from either a +3.3V or a +5V
power supply. With a 3.3V power supply the chipset
dissipates only 1W typically.
Figure 1 shows a typical network configuration incor-
porating the chipset. The chipset is compatible with
AMCC’s S2036 Open Fiber Control (OFC) device.
Figure 1. System Block Diagram
S2036
Open
Fiber
Control
(OFC)
Fibre
Channel
Controller
S2042
TX
S2043
RX
Optical
TX
Optical
RX
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
Optical
RX
Optical
TX
S2043
RX
S2042
TX
S2036
Open
Fiber
Control
(OFC)
Fibre
Channel
Controller
1




S2042 pdf, 반도체, 판매, 대치품
S2042/S2043
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Figure 5. Functional Waveform
S REFCLK
2 (Input)
0
PARALLEL
4 DATA BUS
2 (Input)
K28.5,
Byte 1
of Data
Byte 2, 3
of Data
Byte 4, 5
of Data
Byte 6, 7 Byte 8, 9 Byte 10, Byte 12, Byte 14,15 K28.5
of Data of Data 11 of Data 13 of Data of Data Byte 16
of Data
SERIAL DATA
S RCLK
2 (Output)
0 SYNC
(Output)
4 PARALLEL
3 DATA BUS
(Output)
K28.5 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 K28.5 D16
K28.5,
Byte 1
of Data
Byte 2, 3 Byte 4, 5 Byte 6, 7 Byte 8, 9 Byte 10, Byte 12, Byte 14,15
of Data of Data of Data of Data 11 of Data 13 of Data of Data
Table 3. Data Mapping to 8b/10b Alphabetic Representation
TX[00:19] or
RX[00:19]
8b/10b alphabetic
representation
First Data Byte
Second Data Byte
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
abcdei f ghj abcdei f ghj
First bit received in 20-bit mode
First bit received in 10-bit mode
S2043 RECEIVER FUNCTIONAL
DESCRIPTION
The S2043 receiver is designed to implement the
ANSI X3T11 Fibre Channel specification receiver
functions. A block diagram showing the basic chip
function is provided in Figure 4.
Whenever a signal is present, the S2043 attempts to
achieve synchronization on both bit and transmis-
sion-word boundaries of the received encoded bit
stream. Received data from the incoming bit stream
is provided on the device’s parallel data outputs.
The S2043 accepts serial encoded data from a fiber
optic or coaxial cable interface. The serial input stream
is the result of the serialization of 8B/10B encoded
data by an FC compatible transmitter. Clock recov-
ery is performed on-chip, with the output data
presented to the Fibre Channel transmission layer
as 10- or 20-bit parallel data. The chip is program-
mable to operate at the Fibre Channel specified
operating frequencies of 1062, 531 and 266 Mbit/s.
Serial/Parallel Conversion
Serial data is received on the RX, RY pins. The PLL
clock recovery circuit will lock to the data stream if the
clock to be recovered is within ±100 PPM of the inter-
nally generated bit rate clock. The recovered clock is
used to retime the input data stream. The data is
then clocked into the serial to parallel output regis-
ters on the low going edge of RCLK. In 1062 Mbit/
sec, 10-bit mode, data is clocked out on the falling
edge of RCLK and RCLKN.The parallel data out can
be either 10 or 20 bits wide determined by the state
of the DWS pin. The word clock (RCLK) is synchro-
nized to the incoming data stream word boundary by
the detection of the fiber channel K28.5 synchroniza-
tion pattern (0011111010, positive running disparity).
10-Bit/20-Bit Mode
The S2043 will operate with either 10-bit or 20-bit
parallel data outputs. This option is selectable via
the DWS pin. See Table 4. In 10-bit mode, D10-D19
are used and D0-D9 are driven to the logic high state.
Reference Clock Input
The reference clock input must be supplied with a single-
ended AC coupled crystal clock source at ±100 PPM
tolerance. See Table 4 for reference clock frequencies.
Framing
The S2043 provides SYNC character recognition and
data word alignment of the TTL level compatible output
data bus. In systems where the SYNC detect function
is undesired, a LOW on the SYNCEN input disables
the SYNC function and the data will be “un-framed”.
Applied Micro Circuits Corporation
4 6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333

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S2042 전자부품, 판매, 대치품
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
S2042/S2043
S2042 Pin Assignment and Descriptions (Continued)
Pin Name Level I/O Pin # Description
OE0
OE1
REFSEL
RATESEL
Static
TTL
TTL
Static
Multi-
TTL
I
I
I
I
ECLVCC
TTL
+3.3V
TTLGND
TTLVCC
ECLIOVCC
ECLIOVEE
AVCC
AVEE
ECLVEE
GND
+3.3V/
+5V
+3.3V
GND
+3.3V
GND
GND
2 Active low output-enable control for TX/TY outputs. TX/TY will
go to the logic low state when disabled.
1 Active low output-enable control for TLX/TLY outputs. TLX/TLY
will go to the logic low state when disabled.
18 Multilevel input used to select the reference clock frequency.
(See Table 1.)
15 Multilevel input used to select the operating speed of the
transmitter. (See Table 1.)
21, 39,
45
14
17
Core +3.3V
TTL Ground
TTL Power Supply (+5V if TTL)
3, 10
6, 7
27, 32
26, 33
13, 34,
40, 46,
51, 52
PECL I/O Power Supply
PECL I/O Power Supply
Analog Power Supply
Analog Ground
Core Ground
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
7

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