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부품번호 AD73511 기능
기능 Low-power CMOS Analog Front End
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AD73511 데이터시트, 핀배열, 회로
www.DataSheet4U.com
a
Low-Power CMOS Analog Front End
with Flash based DSP Microcomputer
Preliminary Technical Data
AD73511
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AFE PERFORMANCE
16-Bit A/D Converter
16-Bit D/A Converter
POWER-DOWN
CONTROL
Programmable Input/Output Sample Rates
77 dB ADC SNR
77 dB DAC SNR
64 kS/s Maximum Sample Rate
DATA
ADDRESS
GENERATORS
DAG1 DAG2
PROGRAM
SEQUENCER
MEMORY
16K PM 16K DM
(OPTIONAL (OPTIONAL
8K) 8K)
PROGRAM MEMORY ADDRESS
PROGRAMMABLE
I/O
AND
FLAGS
FULL MEMORY
MODE
EXTERNAL
ADDRESS
BUS
–90 dB Crosstalk
Low Group Delay (25 µs typ per ADC Channel,
50 µs typ per DAC Channel)
YProgrammable Input/Output Gain
ROn-Chip Reference
ADSP PERFORMANCE
19 ns Instruction Cycle Time @ 3.3 Volts, 52 MIPS
IN LSustained Performance
AD73511-80
IM A80K Bytes of On-Chip RAM, Configured as 16K Words
L ICProgram Memory RAM and 16K Words
Data Memory RAM
E NAD73511-40
PR H40K Bytes of On-Chip RAM, Configured as 8K Words
C AProgram Memory RAM and 8K Words
E TData Memory RAM
T AFLASH Memory
64 kbytes
DWritable in pages of 128 bytes
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
ADSP-2100 BASE
ARCHITECTURE
REF
SERIAL PORTS
SPORT 0 SPORT 1
SERIAL PORT
SPORT 2
TIMER
ADC
DAC
ANALOG FRONT END
SECTION
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
FLASH
MEMORY
64 KBYTES
The sampling rate of the AFE is programmable with four
Fast Page Write Cycle of 5 ms (typical)
separate settings offering 64, 32, 16 and 8 kHz sampling rates
(from a master clock of 16.384 MHz) while the serial port
(SPORT2) allows easy expansion of the number of I/O
GENERAL DESCRIPTION
channels by cascading extra AFEs external to the AD73511.
The AD73511 is a single-device incorporating a single analog
front end, microcomputer optimized for digital signal
processing (DSP) and a FLASH based boot memory for the
DSP.
The AD73511’s DSP engine combines the ADSP-2100
family base architecture (three computational units, data
address generators and a program sequencer) with two serial
ports, a 16-bit internal DMA port, a byte DMA port, a
The AD73511’s analog front end (AFE) section is suitable
programmable timer, Flag I/O, extensive interrupt capabilities
for general purpose applications including speech and
and on-chip program and data memory.
telephony. The AFE section features a 16-bit A/D converter
and a 16-bit D/A converter. Each converter provides 77 dB
signal-to-noise ratio over a voiceband signal bandwidth.
The AD73511-80 integrates 80K bytes of on-chip memory
configured as 16K words (24-bit) of program RAM, and 16K
words (16-bit) of data RAM. The AD73511-40 integrates
The AD73511 is particularly suitable for a variety of applica- 40K bytes of on-chip memory configured as 8K words (24-
tions in the speech and telephony area including low bit rate, bit) of program RAM, and 8K words (16-bit) of data RAM.
high quality compression, speech enhancement, recognition
Both devices feature a Flash memory array of 64 kbytes (512
and synthesis. The low group delay characteristic of the AFE kbits) connected to the DSP’s byte-wide DMA port
makes it suitable for single or multichannel active control
(BDMA). This allows non-volatile storage of the DSP’s boot
applications. The A/D and D/A conversion channels feature
code and system data parameters. Power-down circuitry is
programmable input/ouput gains with ranges 38 dB and 21 also provided to meet the low power needs of battery
dB respectively. An on-chip reference voltage is included
operated portable equipment. The AD73511 is available in a
to allow single supply operation.
119-ball PBGA package.
REV. PrA 08/99
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1998




AD73511 pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
AD73511–SPECIFICATIONS (AVDD = DVDD = +3.0V to 3.6V; DGND = AGND = 0 V, fMCLK = 16.384 MHz,
fSAMP = 64 kHz; TA = TMIN to TMAX, unless otherwise noted)
PARAMETER
Min Typ Max Units Test Conditions
AFE SECTION
REFERENCE
REFCAP
Absolute Voltage, VREFCAP
REFCAP TC
REFOUT
Typical Output Impedance
Absolute Voltage, VREFOUT
Minimum Load Resistance
Maximum Load Capacitance
1.08 1.2 1.32 V
50 ppm/°C 0.1 µF Capacitor Required from
REFCAP to AGND2
145
1.08 1.2 1.32 V
Unloaded
1 k
100 pF
ADC SPECIFICATIONS
Maximum Input Range at VIN2, 3
1.578
V p-p Measured Differentially.
–2.85
dBm Max. Input = (1.578/1.2)*VREFCAP
Nominal Reference Level at VIN
(0 dBm0)
Absolute Gain
YPGA = 0 dB
RPGA = 38 dB
AGain Tracking Error
INSignal to (Noise + Distortion)
LPGA = 0 dB
ELIM ICAPGA = 38 dB
PR HNTotal Harmonic Distortion
C APGA = 0 dB
E TPGA = 38 dB
T AIntermodulation Distortion
DIdle Channel Noise
1.0954
–6.02
V p-p Measured Differentially
dBm
–2.2 -0.6 +1.0 dB
–1.0 dB
±0.1
dB
70 76
70 74
72
56
60
dB
dB
dB
dB
dB
59
1.0 kHz, 0 dBm0
1.0 kHz, 0 dBm0
1.0 kHz, +3 dBm0 to –50 dBm0
Refer to Figure 5
300 Hz to 3400 Hz;
0 Hz to fSAMP/2;
300 Hz to 3400 Hz; fSAMP = 64 kHz
0 Hz to fSAMP/2; fSAMP = 64 kHz
300 Hz to 3400 Hz;
dB 0 Hz to fSAMP/2
–85 –70 dB 300 Hz to 3400 Hz;
–85 dB 300 Hz to 3400 Hz;
–82 dB PGA = 0 dB
–76 dBm0 PGA = 0 dB
Crosstalk
–100
dB ADC Input Level: 1.0kHz, 0 dBm0
DAC Input at Idle
DC Offset
–20 +2 +25 mV PGA = 0 dB
Power Supply Rejection
–84 dB Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
Group Delay4, 5
Input Resistance at PGA2, 4, 6
25 µs fSAMP = 64 kHz
45 kDMCLK = 16.384 MHz
DAC SPECIFICATIONS
Maximum Voltage Output Swing2
Single Ended
Differential
Nominal Voltage Output Swing (0 dBm0)
Single-Ended
Differential
Output Bias Voltage
Absolute Gain
Gain Tracking Error
Signal to (Noise + Distortion) at 0 dBm0
PGA = 0 dB
PGA = 6 dB
1.578
–2.85
3.156
3.17
V p-p
dBm
V p-p
dBm
PGA = 6 dB
Max. Output = (1.578/1.2)*VREFCAP
PGA = 6 dB
Max. Output = 2*((1.578/1.2)*VREFCAP)
1.0954
V p-p PGA = 6 dB
–6.02
dBm
2.1909
V p-p PGA = 6 dB
0 dBm
1.08 1.2 1.32 V
REFOUT Unloaded
–1.8 -0.7 +0.4 dB 1.0 kHz, 0 dBm0; Unloaded
± 0.1
dB 1.0 kHz, +3 dBm0 to –50 dBm0
70 77
dB 300 Hz to 3400 Hz
76 dB 300 Hz to 3400 Hz; fSAMP = 64 kHz
77 dB 300 Hz to 3400 Hz;
77 dB 300 Hz to 3400 Hz; fSAMP = 64 kHz
–4– REV. PrA 08/99

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AD73511 전자부품, 판매, 대치품
www.DataSheet4U.com
Preliminary Technical Data
AD73511
POWER CONSUMPTION
CONDITIONS
Typ. Max. SE MCLK On Test Conditions
AFE SECTION
ADC On Only
7 7.2 1 YES
REFOUT Disabled
ADC and DAC On
11 12 1 YES
REFOUT Disabled
REFCAP On Only
0.65 1.00 0 NO
REFOUT Disabled
REFCAP and
2.7 3.8 0 NO
REFOUT On Only
All AFE Sections Off
0.6 0.65 0 YES
MCLK Active Levels Equal to 0V
and DVDD
All AFE Sections Off
2 µA 10 µA 0 NO
Digital Inputs Static and Equal to
0 V or DVDD
DSP SECTION
Idle Mode
6.4 - -
Dynamic
43
The above values are in mA and are typical values unless otherwise noted.
--
TIMING CHARACTERISTICS - AFE SECTION INARYLParameter
IM AClock Signals
L ICt1
Et2
R Nt3
P HSerial Port
C At4
E Tt5
T At6
Dt7
Limit Units Description
See Figure 1
61 ns min 16.384 MHz MCLK Period
24.4 ns min MCLK Width High
24.4 ns min MCLK Width Low
See Figures 3 and 4
t1 ns min SCLK Period (SCLK = MCLK)
0.4 * t1 ns min SCLK Width High
0.4 * t1 ns min SCLK Width Low
20 ns min SDI/SDIFS Setup Before SCLK Low
t8 0 ns min SDI/SDIFS Hold After SCLK Low
t9 10 ns max SDOFS Delay From SCLK High
t10 10 ns min SDOFS Hold After SCLK High
t11 10 ns min SDO Hold After SCLK High
t12 10 ns max SDO Delay From SCLK High
t13 30 ns max SCLK Delay from MCLK
REV. PrA 08/99
–7–

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AD73511

Low-power CMOS Analog Front End

Analog Devices
Analog Devices

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