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부품번호 AD73522 기능
기능 Dual Analog Front End
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AD73522 데이터시트, 핀배열, 회로
www.DataSheet4U.com
a
Dual Analog Front End
with Flash based DSP Microcomputer
Preliminary Technical Data
AD73522
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AFE PERFORMANCE
Two 16-Bit A/D Converters
78 dB ADC SNR
Two 16-Bit D/A Converters
77 dB DAC SNR
DATA ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
POWER-DOWN
CONTROL
MEMORY
16K PM
(OPTIONAL 8K)
16K DM
(OPTIONAL 8K)
Programmable Input/Output Sample Rates
64 kS/s Maximum Sample Rate
PROGRAM MEMORY ADDRESS
Programmable Input/Output Gain
DATA MEMORY ADDRESS
On-Chip Reference
DSP PERFORMANCE
Y19 ns Instruction Cycle Time @ 3.3 Volts, 52 MIPS
RSustained Performance
AAD73522-80
80K Bytes of On-Chip RAM, Configured as 16K Words
IN LProgram Memory RAM and 16K Words
Data Memory RAM
IM AAD73522-40
L IC40K Bytes of On-Chip RAM, Configured as 8K Words
Program Memory RAM and 8K Words
E NData Memory RAM
PR HFLASH Memory
C A64 kbytes
E TWritable in pages of 128 bytes
T DAFast Page Write Cycle of 5 ms (typical)
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
ADSP-2100 BASE
ARCHITECTURE
SERIAL PORTS
SPORT 0 SPORT 1
SERIAL PORT
REF
SPORT 2
ADC1
DAC1
ADC2
ANALOG FRONT END
SECTION
PROGRAMMABLE
I/O
AND
FLAGS
TIMER
DAC2
FULL MEMORY
MODE
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
FLASH
Byte Memory
64 kbytes
GENERAL DESCRIPTION
The AD73522 is a single-device incorporating a dual analog
front end, microcomputer optimized for digital signal
processing (DSP) and a FLASH based boot memory for the
DSP.
The AD73522’s analog front end (AFE) section features a
dual front-end converter for general purpose applications
including speech and telephony. The AFE section features
two 16-bit A/D conversion channels and two 16-bit D/A
conversion channels. Each channel provides 77 dB signal-to-
noise ratio over a voiceband signal bandwidth. It also features
an input to output gain network in both the analog and digital
domains. This is featured on both codecs and can be used for
impedance matching or scaling when interfacing to Subscriber
Line Interface Circuits (SLICs)
The AD73522 is particularly suitable for a variety of applica-
tions in the speech and telephony area including low bit rate,
high quality compression, speech enhancement, recognition
and synthesis. The low group delay characteristic of the AFE
makes it suitable for single or multichannel active control
applications. The A/D and D/A conversion channels feature
REV. PrC 05/99
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
programmable input/ouput gains with ranges 38 dB and 21
dB respectively. An on-chip reference voltage is included
to allow single supply operation.
The AD73522’s DSP engine combines the ADSP-2100
family base architecture (three computational units, data
address generators and a program sequencer) with two serial
ports, a 16-bit internal DMA port, a byte DMA port, a
programmable timer, Flag I/O, extensive interrupt capabilities
and on-chip program and data memory.
The AD73522-80 integrates 80K bytes of on-chip memory
configured as 16K words (24-bit) of program RAM, and 16K
words (16-bit) of data RAM. The AD73522-40 integrates
40K bytes of on-chip memory configured as 8K words (24-
bit) of program RAM, and 8K words (16-bit) of data RAM.
Both devices feature a Flash memory array of 64 kbytes (512
kbits) connected to the DSP’s byte-wide DMA port
(BDMA). This allows non-volatile storage of the DSP’s boot
code and system data parameters. Power-down circuitry is
also provided to meet the low power needs of battery
operated portable equipment. The AD73522 is available in a
119-ball PBGA package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1998




AD73522 pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
AD73522–SPECIFICATIONS (AVDD = DVDD = +3.0V to 3.6V; DGND = AGND = 0 V, fMCLK = 16.384 MHz,
fSAMP = 64 kHz; TA = TMIN to TMAX, unless otherwise noted)
PARAMETER
Min Typ Max Units Test Conditions
AFE SECTION
REFERENCE
REFCAP
Absolute Voltage, VREFCAP
REFCAP TC
REFOUT
Typical Output Impedance
Absolute Voltage, VREFOUT
Minimum Load Resistance
Maximum Load Capacitance
1.08 1.2 1.32 V
50 ppm/°C 0.1 µF Capacitor Required from
REFCAP to AGND2
130 W
1.08 1.2 1.32 V
Unloaded
1 kW
100 pF
INPUT AMPLIFIER
Offset
±1.0
mV
Maximum Output swing
1.578
V Max. Output Swing =(1.578/1.2)*VREFCAP
Feedback Resistance
Feedback Capacitance
YANALOG GAIN TAP
RGain at Max. Setting
Gain at Min. Setting
AGain Resolution
INGain Accuracy
LSettling Time
IM ADelay
L ICADC SPECIFICATIONS
EMaximum Input Range at VIN2, 3
PR HNNominal Reference Level at VIN
C A(0 dBm0)
E TAbsolute Gain
T APGA = 0 dB
DPGA = 38 dB
50 kW fC = 32 kHz
100 pF
+1
-1
5
±1.0
1.0
0.5
Bits Gain Step Size = 0.0625
% Output Unloaded
ms Tap Gain Change of -FS to +FS
ms
1.578
–2.85
1.0954
–6.02
V p-p
dBm
V p-p
dBm
Measured Differentially.
Max. Input = (1.578/1.2)*VREFCAP
Measured Differentially
–0.5 0.4 +1.2 dB
–1.5 –0.7 +0.1 dB
1.0 kHz, 0 dBm0
1.0 kHz, 0 dBm0
Gain Tracking Error
±0.1
dB 1.0 kHz, +3 dBm0 to –50 dBm0
Signal to (Noise + Distortion)
Refer to Figure 5
PGA = 0 dB
PGA = 38 dB
Total Harmonic Distortion
72 78
78
55 57
52 56
dB 300 Hz to 3400 Hz; fSAMP = 64 kHz
dB 300 Hz to 3400 Hz; fSAMP = 8 kHz
dB 0 Hz to fSAMP/2; fSAMP = 64 kHz
dB 300 Hz to 3400 Hz; fSAMP = 64 kHz
PGA = 0 dB
PGA = 38 dB
Intermodulation Distortion
–84 –73 dB
–70 –60 dB
–65 dB
300 Hz to 3400 Hz; fSAMP = 64 kHz
300 Hz to 3400 Hz; fSAMP = 64 kHz
PGA = 0 dB
Idle Channel Noise
–71 dBm0 PGA = 0 dB
Crosstalk, ADC-to-DAC
–100
dB ADC Input Level: 1.0kHz, 0 dBm0
DAC Input at Idle
ADC-to-ADC
-100 dB ADC1 Input Level: 1.0kHz, 0 dBm0
ADC2 Input at Idle. Input Amps bypassed
-70 dB Input Amplifiers included in input channel
DC Offset
–30 +10 +45 mV PGA = 0 dB
Power Supply Rejection
–65 dB Input Signal Level at AVDD and DVDD
Pins: 1.0 kHz, 100 mV p-p Sine Wave
Group Delay4, 5
25 µs
Input Resistance at PGA2, 4, 6
20 kW DMCLK = 16.384 MHz; Input Amplifiers
bypassed and AGT off
DIGITAL GAIN TAP
Gain at Max. Setting
Gain at Min. Setting
Gain Resolution
Delay
Settling Time
+1
-1
16 Bits Tested to 5 MSBs of settings
25 ms Includes DAC delay
100 ms Tap Gain Change from -FS to +FS;
Includes DAC settling time
–4– REV. PrC 05/99

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AD73522 전자부품, 판매, 대치품
www.DataSheet4U.com
Preliminary Technical Data
AD73522
POWER CONSUMPTION
CONDITIONS
Typ. Max. SE MCLK On Test Conditions
AFE SECTION
ADCs On Only
11.5 12 1 YES
REFOUT Disabled
DACs On Only
20 22 1 YES
REFOUT Disabled
ADCs and DACs On
24.5 27 1 YES
REFOUT Disabled
ADCs and DACs
30 34 1 YES
REFOUT Disabled
and Input Amps On
ADCs and DACs
29 32.5 1 YES
REFOUT Disabled
and AGT On
All Sections On
37 42 1 YES
REFCAP On Only
0.8 1.25 0 NO
REFOUT Disabled
REFCAP and
3.5 4.5 0 NO
REFOUT On Only
All AFE Sections Off
1.5 1.8 0
YAll AFE Sections Off
10 µA 40 µA 0
RFlash SECTION
ARead Mode
INWrite Mode
LStandby Current
IM AThe above values are in mA and are typical values unless otherwise noted.
12
15
15 µA
YES
NO
MCLK Active Levels Equal to 0V
and DVDD
Digital Inputs Static and Equal to
0 V or DVDD
BMS = RD = 0; WR = 1
BMS = WR = 0; RD = 1
BMS = RD = WR = 1
TIMING CHARACTERISPTICSR- AEFE SLECCTIOHN NICAParameter
TE ATClock Signals
Dt1
Limit
61
Units Description
See Figure 1
ns min 16.384 MHz MCLK Period
t2 24.4 ns min MCLK Width High
t3 24.4 ns min MCLK Width Low
Serial Port
See Figures 3 and 4
t4 t1 ns min SCLK Period (SCLK = MCLK)
t5 0.4 * t1 ns min SCLK Width High
t6 0.4 * t1 ns min SCLK Width Low
t7 20 ns min SDI/SDIFS Setup Before SCLK Low
t8 0 ns min SDI/SDIFS Hold After SCLK Low
t9 10 ns max SDOFS Delay From SCLK High
t10 10 ns min SDOFS Hold After SCLK High
t11 10 ns min SDO Hold After SCLK High
t12 10 ns max SDO Delay From SCLK High
REV. PrC 05/99
–7–

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