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PDF AD7352 Data sheet ( Hoja de datos )
| Número de pieza | AD7352 | |
| Descripción | SAR ADC | |
| Fabricantes | Analog Devices | |
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Data Sheet
Differential Input, Dual, Simultaneous
Sampling, 3 MSPS, 12-Bit, SAR ADC
AD7352
FEATURES
Dual 12-bit SAR ADC
Simultaneous sampling
Throughput rate: 3 MSPS per channel
Specified for VDD at 2.5 V
No conversion latency
Power dissipation: 26 mW at 3 MSPS
On-chip reference: 2.048 V ± 0.25%, 6 ppm/°C
Dual conversion with read
High speed serial interface: SPI-/QSPI™-/MICROWIRE™-/ DSP-
compatible
−40°C to +125°C operation
Available in a 16-lead TSSOP
APPLICATIONS
Data acquisition systems
Motion control
I and Q demodulation
GENERAL DESCRIPTION
The AD73521 is a dual, 12-bit, high speed, low power, successive
approximation ADC that operates from a single 2.5 V power
supply and features throughput rates up to 3 MSPS. The part
contains two ADCs, each preceded by a low noise, wide band-
width track-and-hold circuit that can handle input frequencies
in excess of 110 MHz.
The conversion process and data acquisition use standard
control inputs allowing for easy interfacing to microprocessors
or DSPs. The input signal is sampled on the falling edge of CS;
and a conversion is also initiated at this point. The conversion
time is determined by the SCLK frequency.
The AD7352 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. With a 2.5 V
supply and a 3 MSPS throughput rate, the part consumes 10 mA
typically. The part also offers a flexible power/throughput rate
management options.
The analog input range for the part is the differential common-
mode ±VREF/2. The AD7352 has an on-chip 2.048 V reference
that can be overdriven when an external reference is preferred.
The AD7352 is available in a 16-lead thin shrink small outline
package (TSSOP).
VINA+
VINA–
REFA
FUNCTIONAL BLOCK DIAGRAM
VDD
VDRIVE
AD7352
T/H
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
SDATAA
REF
BUF
BUF
CONTROL
LOGIC
SCLK
CS
REFB
VINB+
VINB–
12-BIT
SUCCESSIVE
T/H
APPROXIMATION
ADC
SDATAB
AGND
AGND
REFGND
Figure 1.
DGND
PRODUCT HIGHLIGHTS
1. Two Complete ADC Functions.
These functions allow simultaneous sampling and conversion
of two channels. The conversion result of both channels is
simultaneously available on separate data lines or in suc-
cession on one data line if only one serial port is available.
2. High Throughput With Low Power Consumption.
The AD7352 offers a 3 MSPS throughput rate with 26 mW
power consumption.
3. No Conversion Latency.
The AD7352 features two standard successive
approximation ADCs with accurate control of the sampling
instant via a CS input and, once off, conversion control.
Table 1. Related Devices
Generic Resolution Throughput
AD7356 12-bit
5 MSPS
AD7357 14-bit
4.2MSPS
AD7266 12-bit
2 MSPS
AD7866 12-bit
1 MSPS
AD7366 12-bit
1 MSPS
AD7367 14-bit
1 MSPS
Analog Input
Differential
Differential
Differential/single-ended
Single-ended
Single-ended bipolar
Single-ended bipolar
1 Protected by U.S. Patent No. 6,681,332.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2008–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD7352
Data Sheet
Parameter
LOGIC INPUTS
Input High Voltage (VINH)
Input Low Voltage (VINL)
Input Current (IIN)
Input Capacitance (CIN)
LOGIC OUTPUTS
Output High Voltage (VOH)
Output Low Voltage (VOL)
Floating-State Leakage Current
Floating-State Output Capacitance
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time2
Throughput Rate
POWER REQUIREMENTS3
VDD
VDRIVE
ITOTAL4
Normal Mode (Operational)
Normal Mode (Static)
Partial Power-Down Mode
Full Power-Down Mode
Power Dissipation
Normal Mode (Operational)
Normal Mode (Static)
Partial Power-Down Mode
Full Power-Down Mode
Min
Typ Max
Unit
0.6 × VDRIVE
3
0.3 × VDRIVE
±1
V
V
μA
pF
VDRIVE − 0.2
0.2
±1
5.5
Straight binary
V
V
μA
pF
t2 + 13 × tSCLK
ns
30 ns
3 MSPS
2.25 2.75 V
2.25 3.6 V
10 15
6 7.5
3.5 4.5
5 40
90
mA
mA
mA
μA
μA
26 45
16 21
9.5 11.5
16 110
250
mW
mW
mW
μW
μW
1 Temperature ranges are as follows: Y grade: −40°C to +125°C; B grade: −40°C to +85°C.
2 See the Terminology section.
3 Current and power typical specifications are based on results with VDD = 2.5 V and VDRIVE = 3.0 V.
4 ITOTAL is the total current flowing in VDD and VDRIVE.
Test Conditions/Comments
VIN = 0 V or VDRIVE
Full-scale step input, settling to 0.5 LSBs
Nominal VDD = 2.5 V
Digital inputs = 0 V or VDRIVE
SCLK on or off
SCLK on or off
SCLK on or off, −40°C to +85°C
SCLK on or off, 85°C to 125°C
SCLK on or off
SCLK on or off
SCLK on or off, −40°C to +85°C
SCLK on or off, 85°C to 125°C
Rev. B | Page 4 of 20
5 Page 
AD7352
Data Sheet
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale (1 LSB below
the first code transition) and full scale (1 LSB above the last
code transition).
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Negative Full-Scale Error
Negative full-scale error is the deviation of the first code
transition (00 … 000) to (00 … 001) from the ideal (that is,
−VREF + 0.5 LSB) after the midscale error has been adjusted out.
Negative Full-Scale Error Match
Negative full-scale error match is the difference in negative full-
scale error between the two ADCs.
Midscale Error
Midscale error is the deviation of the midscale code transition
(011 … 111) to (100 … 000) from the ideal (that is, 0 V).
Midscale Error Match
Midscale error match is the difference in midscale error
between the two ADCs.
Positive Full-Scale Error
Positive full-scale error is the deviation of the last code
transition (111 … 110) to (111 … 111) from the ideal (that is,
VREF − 1.5 LSB) after the midscale error has been adjusted out.
Positive Full-Scale Error Match
Positive full-scale error match is the difference in positive full-
scale error between the two ADCs.
ADC-to-ADC Isolation
ADC-to-ADC isolation is a measure of the level of crosstalk
between ADC A and ADC B. It is measured by applying a full-
scale 1 MHz sine wave signal to one of the two ADCs and
applying a full-scale signal of variable frequency to the other
ADC. The ADC-to-ADC isolation is defined as the ratio of the
power of the 1 MHz signal on the converted ADC to the power
of the noise signal on the other ADC that appears in the FFT.
The noise frequency on the unselected channel varies from
100 kHz to 2.5 MHz.
Power Supply Rejection Ratio (PSRR)
PSRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV p-p sine wave
applied to the ADC VDD supply of frequency, fS. The frequency
of the input varies from 5 kHz to 25 MHz.
PSRR (dB) = 10 log(Pf/PfS)
where:
Pf is the power at frequency, f, in the ADC output.
PfS is the power at frequency, fS, in the ADC output.
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC output
at full-scale frequency, f, to the power of a 100 mV p-p sine
wave applied to the common-mode voltage of VIN+ and VIN−
of frequency, fS.
CMRR (dB) = 10 log(Pf/PfS)
where:
Pf is the power at frequency, f, in the ADC output.
PfS is the power at frequency, fS, in the ADC output.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns to track mode at the end
of a conversion. The track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±0.5 LSB, after the end of a conversion.
Signal-to-(Noise and Distortion) Ratio (SINAD)
SINAD is the measured ratio of signal-to-(noise and distortion)
at the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digitization
process; the more levels, the smaller the quantization noise.
The theoretical SINAD for an ideal N-bit converter with a sine
wave input is given by
SINAD = (6.02 N + 1.76) dB
Thus, for a 12-bit converter, SINAD is 74 dB and for a 14-bit
converter, SINAD is 86 dB.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7352, it is defined as
THD (dB) = −20 log
V2 2 + V32 + V4 2 + V5 2 + V6 2
V1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Spurious Free Dynamic Range (SFDR)
SFDR is the ratio of the rms value of the next largest component
in the ADC output spectrum (up to fS/2 and excluding dc) to
the rms value of the fundamental. Normally, the value of this
specification is determined by the largest harmonic in the
spectrum, but for ADCs where the harmonics are buried in
the noise floor, it is a noise peak.
Rev. B | Page 10 of 20
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet AD7352.PDF ] | |
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