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KMMR18R86C 데이터시트 PDF




Samsung Semiconductor에서 제조한 전자 부품 KMMR18R86C은 전자 산업 및 응용 분야에서
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부품번호 KMMR18R86C 기능
기능 (KMMR16R8xC / KMMR18R8xC) SDRAM
제조업체 Samsung Semiconductor
로고 Samsung Semiconductor 로고


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KMMR18R86C 데이터시트, 핀배열, 회로
www.DataSheet4U.com
KMMR16R84(6/8/C/G)C
KMMR18R84(6/8/C/G)C
Preliminary
4/6/8/12/16d RIMMTM Module with 128Mb RDRAMs
4/6/8/12/16d RIMMTM Module with 144Mb RDRAMs
Overview
The Rambus® RIMM™ module is a general purpose high-
performance memory subsystem suitable for use in a broad
range of applications including computer memory, personal
computers, workstations, and other applications where high
bandwidth and low latency are required.
The Rambus RIMM module consists of 128Mb/144Mb
Direct Rambus DRAM devices. These are extremely high-
speed CMOS DRAMs organized as 8M words by 16 or 18
bits. The use of Rambus Signaling Level (RSL) technology
permits 600MHz or 800MHz transfer rates while using
conventional system and board design technologies.
RDRAM devices are capable of sustained data transfers at
1.25 ns per two bytes (10ns per 16 bytes).
The RDRAM architecture enables the highest sustained
bandwidth for multiple, simultaneous, randomly addressed,
memory transactions. The separate control and data buses
with independent row and column control yield over 95%
bus efficiency. The RDRAM's 32-banks architecture
supports up to four simultaneous transactions per device.
Features
High speed 800 and 600MHz RDRAM storage
184 edge connector pads with 1mm pad spacing
Maximum module PCB size : 133.5mm x 34.93mm x
1.37mm (5.21x 1.375x 0.05)
Each RDRAM has 32 banks, for a total of 512, 384, 256,
192, or 128 banks on each 256/288MB, 192/216MB,
128/144MB, 96/108MB, or 64/72MB module respectively
Gold plated edge connector pad contacts
Serial Presence Detect(SPD) support
Operates from a 2.5 volt supply (±5%)
Low power and powerdown self refresh modes
Separate Row and Column buses for higher efficiency
RDRAMs use µ−BGA package type
Key Timing Parameters/Part Numbers
The following table lists the frequency and latency bins
available from RIMM modules. An optional ‘S’designator
instead of ‘R’followed by ‘hyphen(-)’indicates low power
modules.
TABLE 1. Part Number by Freq. & Latency
Speed
Organization
I/O trac (Row
Binning Freq. Access
MHz Time) ns
Part Numbera
32M x 16/18
48M x 16/18
64M x 16/18
96M x 16/18
128M x 16/18
-RG6
-RK8
-RM8
-RG6
-RK8
-RM8
-RG6
-RK8
-RM8
-RG6
-RK8
-RM8
-RG6
-RK8
-RM8
600
800
800
600
800
800
600
800
800
600
800
800
600
800
800
53 KMMR16/18R84C-RG6
45 KMMR16/18R84C-RK8
40 KMMR16/18R84C-RM8
53 KMMR16/18R86C-RG6
45 KMMR16/18R86C-RK8
40 KMMR16/18R86C-RM8
53 KMMR16/18R88C-RG6
45 KMMR16/18R88C-RK8
40 KMMR16/18R88C-RM8
53 KMMR16/18R8CC-RG6
45 KMMR16/18R8CC-RK8
40 KMMR16/18R8CC-RM8
53 KMMR16/18R8GC-RG6
45 KMMR16/18R8GC-RK8
40 KMMR16/18R8GC-RM8
a. -S designator is used for modules with lower self-refresh current.
Form Factor
The Rambus RIMM modules are offered in a 184-pad 1mm
edge connector pad pitch form factor suitable for 184 contact
RIMM connectors. The RIMM module is suitable for
desktop and other system applications.
Note: On two sided modules, RDRAMs are also installed on bottem side of PCB.
Figure 1: Rambus RIMM Module without heat spreader
Page 1
Rev.0.9 Apr. 1999




KMMR18R86C pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
KMMR16R84(6/8/C/G)C
KMMR18R84(6/8/C/G)C
Preliminary
4/6/8/12/16d RIMMTM Module with 128Mb RDRAMs
4/6/8/12/16d RIMMTM Module with 144Mb RDRAMs
Signal
RCTM
Pins
A79
RCTMN A81
RDQA8.. A91, B91, A89, B89, A87, B87, A85,
RDQA0 B85, A83
RDQB8.. B61, A61, B63, A63, B65, A65, B67,
RDQB0 A67, B69
RROW2..
RROW0
RSCK
B77, A75, B75
A59
SA0
SA1
SA2
SCL
SDA
SIN
B53
B55
B57
A53
A55
B36
SOUT
A36
SVDD
SWP
VCMOS
Vdd
Vref
A56, B56
A57
A35, B35, A37, B37
A41, A42, A54, A58, B41, B42, B54,
B58
A51, B51
I/O Type Description
I
RSL
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Positive polarity.
I
RSL
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Negative polarity.
Data bus A. A 9-bit bus carrying a byte of read or write
I/O RSL data between the Channel and the RDRAM. RDQA8 is
non-functional on modules x16 RDRAM devices.
Data bus B. A 9-bit bus carrying a byte of read or write
I/O RSL data between the Channel and the RDRAM. RDQB8 is
non-functional on modules x16 RDRAM devices.
I
RSL
Row bus. 3-bit bus containing control and address infor-
mation for row accesses.
I
VCMOS
Serial Clock input. Clock source used to read from and
write to the RDRAM control registers.
I SVDD Serial Presence Detect Address 0.
I SVDD Serial Presence Detect Address 1.
I SVDD Serial Presence Detect Address 2.
I SVDD Serial Presence Detect Clock.
I/O SVDD Serial Presence Detect Data (Open Collector I/O).
Serial I/O for reading from and writing to the control
I/O VCMOS registers. Attaches to SIO0 of the first RDRAM on the
module.
Serial I/O for reading from and writing to the control
I/O VCMOS registers. Attaches to SIO1 of the last RDRAM on the
module.
SPD Voltage. Used for signals SCL, SDA, SWE, SA0,
SA1 and SA2.
I
SVDD
Serial Presence Detect Write Protect (active high). When
low, the SPD can be written as well as read.
CMOS I/O Voltage. Used for signals CMD, SCK, SIN,
SOUT.
Supply voltage for the RDRAM core and interface logic.
Logic threshold reference voltage for RSL signals.
Page 4
Rev.0.9 Apr. 1999

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KMMR18R86C 전자부품, 판매, 대치품
www.DataSheet4U.com
KMMR16R84(6/8/C/G)C
KMMR18R84(6/8/C/G)C
Preliminary
4/6/8/12/16d RIMMTM Module with 128Mb RDRAMs
4/6/8/12/16d RIMMTM Module with 144Mb RDRAMs
AC Electrical Specifications
Symbol
Z
TPD
Parameter and Conditions
Module Impedance
Propagation Delay, all RSL signals
Min
25.2
-
DTPD
DTPD-CMOS
Va/VIN
Propagation delay variation of RSL signals with respect to an average clock
delay b
Propagation delay variation of SCK and CMD signals with respect to an average
clock delay b
Attenuation Limit
-10
-100
VXF/VIN
Forward crosstalk coefficient (300ps input rise time @ 20%-80%)
VXB/VIN
Backward crosstalk coefficient (300ps input rise time @ 20%-80%)
Typ Max Unit
28 30.8 W
See ns
Tablea
10 ps
100 ps
See
Tablea
See
Tablea
See
Tablea
%
%
%
a. Table below lists parameters and specifications for different storage capacity RIMM Modules that use 128Mb or 144Mb RDRAM devices.
b. Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM, CTMN, CFM and CFMN).
AC Electrical Specifications for RIMM Modules
Symbol
TPD
Va/VIN
VXF/VIN
VXB/VIN
RDC
RIMM Module Capacity
No. of 128/144Mb RDRAMs
Parameter and Condition for -800 & -
600 RIMM Modules
Propagation Delay, all RSL signals -800
Propagation Delay, all RSL signals -600
Attenuation Limit -800
Attenuation Limit -600
Forward crosstalk coefficient (300ps input
rise time @ 20%-80%) -800
Forward crosstalk coefficient (300ps input
rise time @ 20%-80%) -600
Backward crosstalk coefficient (300ps
input rise time @ 20%-80%) -800
Backward crosstalk coefficient (300ps
input rise time @ 20%-80%) -600
DC Resistance Limit -800
DC Resistance Limit -600
256/288MB
16
Max
2.06
2.10
25
21
8
8
2.5
2.5
1.2
1.2
192/216MB
12
Max
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
128/144MB
8
Max
1.50
1.60
16
10
4
4
2.0
2.0
0.8
0.8
96/108MB 64/72MB
6 4 Unit
Max Max
TBD
TBD
TBD
TBD
TBD
1.25 ns
1.25 ns
12 %
8%
2%
TBD
2%
TBD
1.5 %
TBD
1.5 %
TBD
TBD
0.6 W
0.6 W
Page 7
Rev.0.9 Apr. 1999

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관련 데이터시트

부품번호상세설명 및 기능제조사
KMMR18R86C

(KMMR16R8xC / KMMR18R8xC) SDRAM

Samsung Semiconductor
Samsung Semiconductor

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