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부품번호 | P89CV51RD2 기능 |
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기능 | (P89CV51Rx2) 8-Bit Low Power 64Kb Flash Microcontroller | ||
제조업체 | NXP Semiconductors | ||
로고 | |||
전체 30 페이지수
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P89CV51RB2/RC2/RD2
8-bit 80C51 5 V low power 64 kB flash microcontroller with
1 kB RAM, SPI, 6-clock CPU with 6/12-clock peripherals
Rev. 01 — 21 May 2007
Product data sheet
1. General description
The P89CV51RB2/RC2/RD2 are 80C51 microcontrollers with 16 kB/32 kB/64 kB flash
and 1 kB of data RAM. These devices are designed to be drop-in and software compatible
replacements for the popular P89C51RB2/RC2/RD2 devices. Both the In-System
Programming (ISP) and In-Application Programming (IAP) boot codes are upward
compatible.
Additional features of the P89CV51RB2/RC2/RD2 device when compared to the
P89C51RB2/RC2/RD2 devices are the inclusion of an SPI interface, and increase in
RAM, and the ability to erase code memory in 128-byte pages.
The IAP capability combined with the 128-byte page size allows for efficient use of the
code memory for non-volatile data storage.
2. Features
2.1 Principal features
Supports 12-clock (default) or 6-clock mode selection via ISP or parallel programmer
6-clock/12-clock mode programmable “on-the-fly” by SFR bit
Peripherals (PCA, timers, UART) may use either 6-clock or 12-clock mode while the
CPU is in 6-clock mode
128-byte page erase for efficient use of code memory as non-volatile data storage
0 MHz to 40 MHz operating frequency in 12x mode, 20 MHz in 6x mode
16/32/64 kB of on-chip flash user code memory with ISP and IAP
1 kB RAM
SPI (Serial Peripheral Interface) and enhanced UART
PCA (Programmable Counter Array) with PWM and Capture/Compare functions
Three 16-bit timers/counters
2.2 Additional features
Four 8-bit I/O ports
WatchDog Timer (WDT)
30 ms page erase, 150 ms block erase
PLCC44 and TQFP44 packages
Ten interrupt sources with four priority levels
Second DPTR register
Low EMI mode (ALE inhibit)
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5. Pinning information
5.1 Pinning
P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
P1[5]/CEX2/MOSI 7
P1[6]/CEX3/MISO 8
P1[7]/CEX4/SPICLK 9
RST 10
P3[0]/RXD 11
n.c. 12
P3[1]/TXD 13
P3[2]/INT0 14
P3[3]/INT1 15
P3[4]/T0 16
P3[5]/T1 17
P89CV51RB2/RC2/RD2
39 P0[4]/AD4
38 P0[5]/AD5
37 P0[6]/AD6
36 P0[7]/AD7
35 EA
34 n.c.
33 ALE
32 PSEN
31 P2[7]/A15
30 P2[6]/A14
29 P2[5]/A13
002aac962
Fig 2. PLCC44 pin configuration
P89CV51RB2_RC2_RD2_1
Product data sheet
Rev. 01 — 21 May 2007
© NXP B.V. 2007. All rights reserved.
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P89CV51RB2/RC2/RD2
80C51 with 1 kB RAM, SPI
Table 3. P89CV51RB2/RC2/RD2 pin description …continued
Symbol
Pin
Type
Description
PLCC44 TQFP44
P1[4]/CEX1/ 6
SS
44 I/O P1[4] — Port 1 bit 4.
I/O CEX1 — Capture/compare external I/O for PCA Module 1
I SS — Slave select input for SPI
P1[5]/CEX2/ 7 1 I/O P1[5] — Port 1 bit 5.
MOSI
I/O CEX2 — Capture/compare external I/O for PCA Module 2
I/O MOSI — Master output/slave input for SPI
P1[6]/CEX3/ 8 2 I/O P1[6] — Port 1 bit 6.
MISO
I/O CEX3 — Capture/compare external I/O for PCA Module 3
I/O MISO — Master input/slave output for SPI
P1[7]/CEX4/ 9 3 I/O P1[7] — Port 1 bit 7.
SPICLK
I/O CEX4 — Capture/compare external I/O for PCA Module 4
I/O SPICLK — Serial clock input/output for SPI
P2[0] to P2[7]
I/O
with
internal
pull-up
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups.
Port 2 pins are pulled HIGH by the internal pull-ups when ‘1’s are
written to them and can be used as inputs in this state. As inputs,
Port 2 pins that are externally pulled LOW will source current (IIL)
because of the internal pull-ups. Port 2 sends the high-order
address byte during fetches from external program memory and
during accesses to external Data Memory that use 16-bit address
(MOVX@DPTR). In this application, it uses strong internal pull-ups
when transitioning to ‘1’s.
P2[0]/A8
24
18
I/O P2[0] — Port 2 bit 0.
O A8 — Address bit 8.
P2[1]/A9
25
19
I/O P2[1] — Port 2 bit 1.
O A9 — Address bit 9.
P2[2]/A10 26 20 I/O P2[2] — Port 2 bit 2.
O A10 — Address bit 10.
P2[3]/A11 27 21 I/O P2[3] — Port 2 bit 3.
O A11 — Address bit 11.
P2[4]/A12 28 22 I/O P2[4] — Port 2 bit 4.
O A12 — Address bit 12.
P2[5]/A13 29 23 I/O P2[5] — Port 2 bit 5.
O A13 — Address bit 13.
P2[6]/A14 30 24 I/O P2[6] — Port 2 bit 6.
O A14 — Address bit 14.
P2[7]/A15 31 25 I/O P2[7] — Port 2 bit 7.
O A15 — Address bit 15.
P3[0] to P3[7]
I/O
with
internal
pull-up
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups.
Port 3 pins are pulled HIGH by the internal pull-ups when ‘1’s are
written to them and can be used as inputs in this state. As inputs,
Port 3 pins that are externally pulled LOW will source current (IIL)
because of the internal pull-ups.
P89CV51RB2_RC2_RD2_1
Product data sheet
Rev. 01 — 21 May 2007
© NXP B.V. 2007. All rights reserved.
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부품번호 | 상세설명 및 기능 | 제조사 |
P89CV51RD2 | (P89CV51Rx2) 8-Bit Low Power 64Kb Flash Microcontroller | NXP Semiconductors |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |