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UC62LV1008 데이터시트 PDF




ETC에서 제조한 전자 부품 UC62LV1008은 전자 산업 및 응용 분야에서
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부품번호 UC62LV1008 기능
기능 LOW POWER CMOS SRAM 128K X 8BITS
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UC62LV1008 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Low Power CMOS SRAM
128K X 8 Bits
UC62LV1008
-55/-70
Features:
• Vcc operation voltage : 1.5V ~ 3.6V
• Low power consumption :
15mA (Max.) operating current
1uA (Typ.) CMOS standby current
• High Speed Access time :
70ns (Max.) at Vcc = 1.5V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Data retention supply voltage as low as 1.2V
• Easy expansion with CE\ and OE\ options
Description
The UC62LV1008 is a high performance, very low power
CMOS Static Random Access Memory organized as 131,072
words by 8 bits and operates from 1.5V to 3.6V supply
voltage. Advanced CMOS technology and circuit techniques
provide both high speed and low power features with a
typical CMOS standby current of 1uA and maximum access
time of 70ns in 1.5V operation.
Easy memory expansion is provided enable (CE\), and
active LOW output enable (OE\) and three-state output
drivers.
The UC62LV1008 has an automatic power down feature,
reducing the power consumption significantly when chip is
deselected.
The UC62LV1008 is available in the JEDEC standard 32 pin
450mil Plastic SOP, 8mmx20.0mm TSOP (type I), and
8mmx13.4mm STSOP.
PRODUCT FAMILY
Product Family
Operating
Tempature
UC62LV1008HC
UC62LV1008FC
UC62LV1008GC
UC62LV1008AC
UC62LV1008HI
UC62LV1008FI
UC62LV1008GI
UC62LV1008AI
0 ~ 70
-40 ~ 85
Vcc Range
1.5V ~ 3.6V
1.5V ~ 3.6V
Speed
(ns)
Vcc=1.5V(Max.)
55/70
55/70
Power Consumption
STANDBY
Operating
Vcc=3.3V(Typ.) Vcc=3.6V(Max.)
1uA 15mA
1uA 15mA
Package
Type
TSOP-32
SOP-32
STSOP-32
DICE
TSOP-32
SOP-32
STSOP-32
DICE
PIN CONFIGURATIONS
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1 32
2 31
3 30
4 29
5 28
6 27
7 26
8 25
9 UC62LV1008FI 24
10 UC62LV1008FC 23
11 22
12 21
13 20
14 19
15 18
16 17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
A11 1
A9 2
A8 3
A13 4
WE 5
CE2
A15
6
7
UC62LV1008HI
VCC 8 UC62LV1008HC
NC 9 UC62LV1008GI
A16 10 UC62LV1008GC
A14 11
A12 12
A7 13
A6 14
A5 15
A4 16
32 OE
31 A10
30 CE
29 DQ7
28 DQ6
27 DQ5
26 DQ4
25 DQ3
24 GND
23 DQ2
22 DQ1
21 DQ0
20 A0
19 A1
18 A2
17 A3
BLOCK DIAGRAM
CE2
CE
WE
OE
ROW
Address
COL
Address
CE
WE
OE
MEMORY ARRAY
128K X 8 Bits
COLUMN DECODER
SENSE AMPLIFIER
&
WRITE DRIVER
X8
I/O BUFFER
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary Rev.1.0
PAGE 1




UC62LV1008 pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
Low Power CMOS SRAM
128K X 8 Bits
UC62LV1008
-55/-70
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Level
VCC/0V
1V/ns
0.5VCC
AC TEST LOADS AND WAVEFORMS
INCLUDING
JIG AND
SCOPE
3.3V
INCLUDING
JIG AND
SCOPE
3.3V
OUTPUT
OUTPUT
FIGURE 1A
FIGURE 1B
TERMINAL EQUIVALENT
667
OUTPUT
1.73V
KEY TO SWITCHING WAVEFORMS
WAVEFORMS
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE
STATE
UNKNOWN
CENTER LINE
IS HIGH
IMPEDANCE
OFF STATE
VCC
GND
ALL INPUT PULSES
10%
90% 90%
10%
FIGURE 2 1V/ns
1V/ns
AC ELECTRICAL CHARACTERISTICS (TA=0
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
tAVAX
tRC
DESCRIPTION
Read Cycle Time
tAVQV
tAA Address Access Time
tELQV
tCE Chip Select Access Time
tGLQV
tOE Output Enable to Output Valid
tELQX
tCLZ Chip Select to Output Low Z
tGLQX
tOLZ Output Enable to Output Low Z
tEHQZ
tCHZ Chip Deselect to Output in High Z
tGHQZ
tOHZ Output Disable to Output in High Z
tAXOX
tOH Address Chang to Output Change
to 70 , VCC=1.5V~3.6V)
UC62LV1008-55
Min Typ Max
55 -
-
UC62LV1008-70
Min Typ Max
70 -
-
UNIT
ns
-
- 55 -
- 70
ns
- - 55 - - 70 ns
- - 30 - - 35 ns
10 -
- 10 -
-
ns
5- - 5 - -
ns
- - 20 -
- 20
ns
- - 20 - - 20 ns
10 -
- 10 -
-
ns
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary Rev.1.0
PAGE 4

4페이지










UC62LV1008 전자부품, 판매, 대치품
www.DataSheet4U.com
Low Power CMOS SRAM
128K X 8 Bits
WRITE CYCLE2(1,6)
ADDRESS
CE
tAS
WE
DOUT
tWC
tAW tCW(11)
tWHZ
tWP(2)
DIN
UC62LV1008
-55/-70
tOH
(7) (8)
tDW tDH
NOTES:
1. WE\ must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE\ and WE\ low. All signals
must be active to initiate a write and any one can terminate a write by going inactive. The data
input setup and hold timing should be referenced to the second transition edge of the signal that
terminates the write.
3. TWR is measured from the earlier of CE\ or WE\ going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to
the outputs must not be applied.
5. If the CE\ low transition occurs simultaneously with the WE\ low transitions or after the WE\
transition, output remain in a high impedance state.
6. OE\ is continuously low (OE\ = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE\ is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE\ going low to the end of write.
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary Rev.1.0
PAGE 7

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부품번호상세설명 및 기능제조사
UC62LV1008

LOW POWER CMOS SRAM 128K X 8BITS

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