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UC62LV4096 데이터시트 PDF




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부품번호 UC62LV4096 기능
기능 Low Power CMOS SRAM
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UC62LV4096 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Low Power CMOS SRAM
256K X 16
UC62LV4096
-55/-70
Features:
• Vcc operation voltage : 1.5 V~ 3.6V
• Low power consumption :
35mA (Max.) operating current
2uA (Typ.) CMOS standby current
• High Speed Access time :
70ns (Max.) at Vcc = 1.5V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Data retention supply voltage as low as 1.2V
• Easy expansion with CE\ and OE\ options
Description
The UC62LV4096 is a high performance, low power
CMOS Static Random Access Memory organized as 262,144
words by 16 and operates from 1.5 V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide
both high speed and low power features with a typical CMOS
standby current of 2uA and maximum access time of 70ns in
1.5V operation.
Easy memory expansion is provided enable (CE\), and
active LOW output enable (OE\) and three-state output
drivers.
The UC62LV4096 has an automatic power down feature,
reducing the power consumption significantly when chip is
deselected.
The US62LV4096 is available in the JEDEC standard 44
pin TSOP (Type II) and 48 pin mini-BGA.
PRODUCT FAMILY
Product Family
Operating
Tempature
UC62LV4096JC
UC62LV4096KC
UC62LV4096AC
UC62LV4096JI
UC62LV4096KI
UC62LV4096AI
0 ~ 70
-40 ~ 85
Vcc Range
1.5V ~ 3.6V
1.5V ~ 3.6V
Speed
(ns)
Vcc=1.5V(Max.)
55/70
55/70
Power Consumption
STANDBY
Operating
Vcc=3.3V(Typ.) Vcc=3.6V(Max.)
2uA 35mA
2uA 35mA
Package
Type
TSOP-44
BGA-48
DICE
TSOP-44
BGA-48
DICE
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
A16
A15
A14
A13
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
UC62LV4096JC
UC62LV4096JI
44 A5
43 A6
42 A7
41 OE
40 UB
39 LB
38 DQ15
37 DQ14
36 DQ13
35 DQ12
34 GND
33 VCC
32 DQ11
31 DQ10
30 DQ9
29 DQ8
28 NC
27 A8
26 A9
25 A10
24 A11
23 A17
LB OE A0 A1 A2 NC
DQ8
UB
A3
A4
CE DQ0
DQ9 DQ10
A5
A6
DQ1
DQ2
GND DQ11
NC
A7
DQ3
VCC
VCC DQ12
NC
A16
DQ4
GND
DQ14 DQ13 A14
A15
DQ5
DQ6
DQ15
NC
A12
A13
WE DQ7
NC A8 A9 A10 A11 A17
BLOCK DIAGRAM
CE
WE
OE
UB
LB
ROW
Address
COL
Address
CE
WE
OE
UB
LB
MEMORY ARRAY
256K X 16 Bits
COLUMN DECODER
SENSE AMPLIFIER
&
WRITE DRIVER
X16
I/O BUFFER
DQ0 ~ DQ15
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary Rev. 1.0
PAGE 1




UC62LV4096 pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
Low Power CMOS SRAM
256K X 16
UC62LV4096
-55/-70
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Level
VCC to 0V
1V/ns
0.5VCC
AC TEST LOADS AND WAVEFORMS
INCLUDING
JIG AND
SCOPE
3.3V
INCLUDING
JIG AND
SCOPE
3.3V
OUTPUT
OUTPUT
FIGURE 1A
FIGURE 1B
TERMINAL EQUIVALENT
667
OUTPUT
1.73V
KEY TO SWITCHING WAVEFORMS
WAVEFORMS
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE
STATE
UNKNOWN
CENTER LINE
IS HIGH
IMPEDANCE
OFF STATE
VCC
GND
ALL INPUT PULSES
10%
90% 90%
10%
FIGURE 2 1V/ns
1V/ns
AC ELECTRICAL CHARACTERISTICS (TA=0
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
tAVAX
tRC
DESCRIPTION
Read Cycle Time
tAVQV
tAA Address Access Time
tELQV
tCE Chip Select Access Time
tBA tBA Data Byte Control Access Time
tGLQV
tOE Output Enable to Output Valid
tELQX
tCLZ Chip Select to Output Low Z
tGLQX
tOLZ Output Enable to Output Low Z
tBE tBE Data Byte Control To Output Low Z
tEHQZ
tCHZ Chip Deselect to Output in High Z
tGHQZ
tOHZ Output Disable to Output in High Z
tBDO tBDO Data Byte Control To Output High Z
tAXOX
tOH Address Chang to Output Change
to 70 , VCC=1.5 V~3.6V)
UC62LV4096-55
Min Typ Max
55 -
-
UC62LV4096-70
Min Typ Max
70 -
-
- - 55 - - 70
- - 55 - - 70
30 35
- - 30 - - 35
10 -
- 10 -
-
5- - 5 - -
10 10
- - 20 -
- 20
- - 20 - - 20
- 20 - 20
10 -
- 10 -
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary Rev. 1.0
PAGE 4

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UC62LV4096 전자부품, 판매, 대치품
www.DataSheet4U.com
Low Power CMOS SRAM
256K X 16
WRITE CYCLE2(1,6)
ADDRESS
CE
tAS
WE
DOUT
tWC
tAW tCW(11)
tWHZ
tWP(2)
DIN
UC62LV4096
-55/-70
tOH
(7) (8)
tDW tDH
NOTES:
1. WE\ must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE\ and WE\ low. All signals
must be active to initiate a write and any one can terminate a write by going inactive. The data
input setup and hold timing should be referenced to the second transition edge of the signal that
terminates the write.
3. TWR is measured from the earlier of CE\ or WE\ going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to
the outputs must not be applied.
5. If the CE\ low transition occurs simultaneously with the WE\ low transitions or after the WE\
transition, output remain in a high impedance state.
6. OE\ is continuously low (OE\ = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE\ is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE\ going low to the end of write.
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Preliminary Rev. 1.0
PAGE 7

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UC62LV4096

Low Power CMOS SRAM

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