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UC62WV0256 데이터시트 PDF




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부품번호 UC62WV0256 기능
기능 Low Power CMOS SRAM 32K X8 Bits
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UC62WV0256 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Low Power CMOS SRAM
32K X8 Bits
UC62WV0256
-35/-55/-70
Features:
• Vcc operation voltage : 2.0V ~ 5.6V
• Low power consumption :
15mA (Max.) operating current
2uA (Typ.) CMOS standby current
• High Speed Access time :
35ns (Max) at Vcc = 2.7V
55ns (Max) at Vcc = 2.7V
70ns (Max.) at Vcc= 2.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Data retention supply voltage as low as 1.2V
• Easy expansion with CE\ and OE\ options
PRODUCT FAMILY
Product Family
Operating
Temperature
UC62WV0256BC
UC62WV0256CC
UC62WV0256DC
UC62WV0256EC
UC62WV0256AC
UC62WV0256BI
UC62WV0256CI
UC62WV0256DI
UC62WV0256EI
UC62WV0256AI
0 ~ 70
~ 85
Vcc Range
2.0V ~ 5.6V
2.0V ~ 5.6V
Description
The UC62WV0256 is a high performance, very low
power CMOS Static Random Access Memory organized as
32,768 words by 8 bits and operates from a wide range of
2.7V to 5.6V supply voltage. Advanced CMOS technology
and circuit techniques provide both high speed and low
power features with a typical CMOS standby current of 1uA
and maximum access time of 70ns in 2.0V operation.
Easy memory expansion is provided enable (CE), and
active LOW output enable (OE) and three-state output
drivers.
The UC62WV0256 has an automatic power down
feature, reducing the power consumption significantly when
chip is deselected.
The UC62WV0256 is available in the JEDEC standard 28 pin
330mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP
and 8mmx13.4mm TSOP (normal type).
Speed
(ns)
Vcc=2.7V
35/55/70
35/55/70
Power Consumption
STANDBY
VCC=5.6V
Operating(Max)
Vcc=5.0V 35ns 55ns 70ns
4uA 25mA 18mA 15mA
4uA 25mA 18mA 15mA
Package
Type
SOP-28
TSOP-28
PDIP-28
SOJ-28
DICE
SOP-28
TSOP-28
PDIP-28
SOJ-28
DICE
PIN CONFIGURATIONS
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1 28
2 27
3 UC62WV0256BI 26
4 UC62WV0256DI 25
5 UC62WV0256EI 24
6 UC62WV0256BC 23
UC62WV0256DC
7 UC62WV0256EC 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
OE
A11
A9
A8
A13
WE
VCC
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
UC62WV0256CC
UC62WV0256CI
28 A10
27 CE
26 DQ7
25 DQ6
24 DQ5
23 DQ4
22 DQ3
21 GND
20 DQ2
19 DQ1
18 DQ0
17 A0
16 A1
15 A2
BLOCK DIAGRAM
CE
WE
OE
ROW
Address
COL
Address
CE
WE
OE
MEMORY ARRAY
32K X 8 Bits
COLUMN DECODER
SENSE AMPLIFIER
&
WRITE DRIVER
X8
I/O BUFFER
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Revision 2.0
PAGE 1




UC62WV0256 pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
Low Power CMOS SRAM
32K X8 Bits
UC62WV0256
-35/-55/-70
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Level
VCC/0V
1V/ns
0.5VCC
AC TEST LOADS AND WAVEFORMS
INCLUDING
JIG AND
SCOPE
3.3V
INCLUDING
JIG AND
SCOPE
3.3V
OUTPUT
OUTPUT
FIGURE 1A
FIGURE 1B
TERMINAL EQUIVALENT
667
OUTPUT
1.73V
KEY TO SWITCHING WAVEFORMS
WAVEFORMS
INPUTS
OUTPUTS
MUST BE
STEADY
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
DON’T CARE
ANY CHANGE
PERMITTED
DOES NOT
APPLY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE
STATE
UNKNOWN
CENTER LINE
IS HIGH
IMPEDANCE
OFF STATE
VCC
GND
ALL INPUT PULSES
10%
90% 90%
10%
FIGURE 2 5ns
5ns
AC ELECTRICAL CHARACTERISTICS (TA=0
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
tAVAX
tRC
DESCRIPTION
Read Cycle Time
tAVQV
tAA Address Access Time
tELQV
tCE Chip Select Access Time
tGLQV
tOE Output Enable to Output Valid
tELQX
tCLZ Chip Select to Output Low Z
tGLQX
tOLZ Output Enable to Output Low Z
tEHQZ
tCHZ Chip Deselect to Output in High Z
tGHQZ
tOHZ Output Disable to Output in High Z
tAXOX
tOH Address Chang to Output Change
to 70 , VCC=3.0V)
UC62WV0256-35
Min Typ Max
35 - -
UC62WV0256-70
Min Typ Max
70 -
-
-
- 35 -
-
70
-
- 35 -
-
70
-
- 15 -
-
50
5 - - 10 -
-
5 - - 10 -
-
0
- 35 0
-
35
0
- 20 0
-
30
10 - - 10 -
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Revision 2.0
PAGE 4

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UC62WV0256 전자부품, 판매, 대치품
www.DataSheet4U.com
Low Power CMOS SRAM
32K X8 Bits
WRITE CYCLE2(1,6)
ADDRESS
CE
tAS
WE
DOUT
tWC
tAW tCW(11)
tWHZ
tWP(2)
DIN
UC62WV0256
-35/-55/-70
tOH
(7) (8)
tDW tDH
NOTES:
1. WE\ must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE\ and WE\ low. All signals
must be active to initiate a write and any one can terminate a write by going inactive. The data
input setup and hold timing should be referenced to the second transition edge of the signal that
terminates the write.
3. TWR is measured from the earlier of CE\ or WE\ going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to
the outputs must not be applied.
5. If the CE\ low transition occurs simultaneously with the WE\ low transitions or after the WE\
transition, output remain in a high impedance state.
6. OE\ is continuously low (OE\ = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE\ is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Revision 2.0
PAGE 7

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UC62WV0256

Low Power CMOS SRAM 32K X8 Bits

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