PDF SSTUM32865 Data sheet ( Hoja de datos )

Número de pieza	SSTUM32865
Descripción	1.8 V 28-bit 1 : 2 registered buffer
Fabricantes	NXP Semiconductors
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No Preview Available ! www.DataSheet4U.com SSTUM32865 1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800 RDIMM applications Rev. 01 — 19 September 2007 Product data sheet 1. General description The SSTUM32865 is a 1.8 V 28-bit 1 : 2 register speciﬁcally designed for use on two rank by four (2R × 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two registers in a single package, thereby freeing up board real-estate and facilitating routing to accommodate high-density Dual In-line Memory Module (DIMM) designs. The SSTUM32865 also integrates a parity function, which accepts a parity bit from the memory controller, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW). It further offers added features over the JEDEC standard register in that it is permanently conﬁgured for high output drive strength. This allows use in high density designs with heavier than normal net loading conditions. Furthermore, the SSTUM32865 features two additional chip select inputs, which allow more versatile enabling and disabling in densely populated memory modules. Both added features (drive strength and chip selects) are fully backward compatible to the JEDEC standard register. The SSTUM32865 is packaged in a 160-ball, 12 × 18 grid, 0.65 mm ball pitch, thin proﬁle ﬁne-pitch ball grid array (TFBGA) package, which, while requiring a minimum 9 mm × 13 mm of board space, allows for adequate signal routing and escape using conventional card technology. 2. Features I 28-bit data register supporting DDR2 I Fully compliant to JEDEC standard for SSTUB32865 I Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two JEDEC-standard DDR2 registers (that is, 2 × SSTUB32864 or 2 × SSTUB32866) I Parity checking function across 22 input data bits I Parity out signal I Controlled multi-impedance output impedance drivers enable optimal signal integrity and speed I Meets or exceeds SSTUB32865 JEDEC standard speed performance I Supports up to 450 MHz clock frequency of operation I Permanently conﬁgured for high output drive I Optimized pinout for high-density DDR2 module design I Chip-selects minimize power consumption by gating data outputs from changing state I Two additional chip select inputs allow optional ﬂexible enabling and disabling 1 page www.DataSheet4U.com NXP Semiconductors SSTUM32865 1.8 V DDR2-800 registered buffer with parity 12 A VREF n.c. B D1 D2 C D3 D4 D D6 D5 E D7 D8 F D11 D9 G D18 D12 H CSGATEEN D15 J CK DCS0 K CK DCS1 L RESET D14 M D0 D10 N D17 D16 P D19 D21 R D13 D20 T DODT1 DODT0 U DCKE0 DCKE1 V VREF MCL 3 PARIN n.c. 4 n.c. n.c. VDDL VDDL VDDL VDDL DCS2 GND DCS3 GND GND VDDL GND GND MCL MCL PTYERR n.c. 5 n.c. n.c. GND GND GND GND GND GND VDDL GND GND VDDL VDDL VDDL MCH MCH 67 QCKE1A QCKE0A QCKE1B QCKE0B n.c. VDDL n.c. VDDR VDDL VDDL VDDR GND Q3B Q3A Q12B Q12A 8 Q21A Q21B GND GND VDDR VDDR GND VDDR GND VDDR GND VDDR VDDR GND Q7B Q7A 160-ball, 12 × 18 grid; top view. An empty cell indicates no ball is populated at that grid point. n.c. denotes a no-connect (ball present but not connected to the die). MCL denotes a pin that must be connected LOW. MCH denotes a pin that must be connected HIGH. Fig 3. Ball mapping 9 Q19A Q19B GND GND VDDR VDDR GND VDDR GND VDDR GND VDDR GND GND Q4B Q4A 10 Q18A Q18B Q13B Q13A 11 12 Q17B Q17A QODT0B QODT0A QODT1B QODT1A Q20B Q20A Q16B Q16A Q1B Q1A Q2B Q2A Q5B Q5A QCS0B QCS0A QCS1B QCS1A Q6B Q6A Q10B Q10A Q9B Q9A Q11B Q11A Q15B Q15A Q14B Q14A Q0B Q8B Q0A Q8A 002aac650 SSTUM32865_1 Product data sheet Rev. 01 — 19 September 2007 © NXP B.V. 2007. All rights reserved. 5 of 28 5 Page www.DataSheet4U.com NXP Semiconductors SSTUM32865 1.8 V DDR2-800 registered buffer with parity RESET DCSn CK m m+1 m+2 m+3 m+4 CK Dn (1) Qn tACT tsu th tPDM, tPDMSS CK to Q PARIN PTYERR tsu th tPHL CK to PTYERR tPHL, tPLH CK to PTYERR 002aaa983 HIGH, LOW, or Don't care HIGH or LOW (1) After RESET is switched from LOW to HIGH, all data and PARIN input signals must be set and held LOW for a minimum time of tACT(max) to avoid false error. Fig 4. RESET switches from LOW to HIGH SSTUM32865_1 Product data sheet Rev. 01 — 19 September 2007 © NXP B.V. 2007. All rights reserved. 11 of 28 11 Page

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