|
|
PDF N2SV6H16FS-6K Data sheet ( Hoja de datos )
| Número de pieza | N2SV6H16FS-6K | |
| Descripción | SDRAM | |
| Fabricantes | Elixir | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de N2SV6H16FS-6K (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
Features
• Fully Synchronous to Positive Clock Edge
• Four Banks controlled by BS0/BS1 (Bank Select)
• Programmable CAS Latency: 2, 3
• Programmable Burst Length: 1, 2, 4, 8, Full page
• Programmable Wrap: Sequential or Interleave
• Burst Read with Single Write Operation
• Automatic and Controlled Precharge Command
N2SV12816FS-6K/75B
N2SV6H16FS-6K/75B
64Mb/128Mb Synchronous DRAM
• Dual Data Mask for byte control (x16)
• Auto Refresh and Self Refresh
• 64ms refresh period (4K cycle)
• JEDEC standard 3.3V Power Supply
• LVTTL compatible
• Package: 54-pin TSOP (II)
Description
The N2SV6H16FS is four-bank Synchronous DRAMs orga-
nized as 1Mbit x 16 I/O x 4 Bank, and N2SV12816FS orga-
nized as 2 Mbit x 16 I/O x 4 Bank. These synchronous
devices achieve high-speed data transfer rates of up to
166MHz by employing a pipeline chip architecture that syn-
chronizes the output data to a system clock.
The device is designed to comply with all JEDEC standards
set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, and data input/out-
put (I/O or DQ) circuits are synchronized with the positive
edge of an externally supplied clock.
RAS, CAS, WE, and CS are pulsed signals which are exam-
ined at the positive edge of each externally applied clock
(CK). Internal chip operating modes are defined by combina-
tions of these signals and a command decoder initiates the
necessary timings for each operation. A fourteen bit address
bus accepts address data in the conventional RAS/CAS mul-
tiplexing style. Twelve row addresses (A0-A11) and two bank
select addresses (BS0, BS1) are strobed with RAS. Eight col-
umn addresses (A0-A8) plus bank select addresses and A10
are strobed with CAS.
Prior to any access operation, the CAS latency, burst length,
and burst sequence must be programmed into the device by
address inputs A0-A7, BS0, BS1 during a mode register set
cycle. In addition, it is possible to program a multiple burst
sequence with single write cycle for write through cache oper-
ation.
Operating the four memory banks in an interleave fashion
allows random access operation to occur at a higher rate
than is possible with standard DRAMs. A sequential and gap-
less data rate of up to 166MHz is possible depending on
burst length, CAS latency, and speed grade of the device.
Simultaneous operation of both decks of a stacked device is
allowed, depending on the operation being done. Auto
Refresh (CBR) and Self Refresh operation are supported.
REV 1.0
08/2006
1
The Document is a general product description and is subject to change without notice.
1 page  
www.DataSheet4U.com
N2SV12816FS-6K/75B
N2SV6H16FS-6K/75B
64Mb/128Mb Synchronous DRAM
Absolute Maximum Ratings
Symbol
VDD
VDDQ
VIN
VOUT
TA
TSTG
PD
IOUT
Parameter
Power Supply Voltage
Power Supply Voltage for Output
Input Voltage
Output Voltage
Operating Temperature (ambient)
Storage Temperature
Power Dissipation
Short Circuit Output Current
Rating
-1.0 to +4.6
-1.0 to +4.6
-1.0 to +4.6
-1.0 to +4.6
0 to +70
-55 to +150
1.0
50
Units
V
V
V
V
°C
°C
W
mA
Notes
1
1
1
1
1
1
1
1
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this spec-
ification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended DC Operating Conditions (TA = 0°C to 70°C)
Symbol
VDD
VDDQ
VIH
VIL
VOH
VOL
Parameter
Supply Voltage
Supply Voltage for Output
Input High Voltage
Input Low Voltage
Output Level (LVTTL)
Output “H” Level Voltage
Output Level (LVTTL)
Output “L” Level Voltage (
Rating
Min. Typ.
3.0 3.3
3.0 3.3
2.0 3.0
-0.3 0
2.4 —
——
1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The overshoot voltage duration is ≤ 3ns.
Max.
3.6
3.6
VDD + 0.3
0.8
—
0.4
Units
V
V
V
V
V
V
Notes
1
2
IOH = -2.0mA
IOL = 2.0mA
Capacitance (TA = 23°C, f = 1MHz, VDD = 3.3V, VREF=1.4+/-200mV )
Symbol
Parameter
Min.
64Mb
Max.
128Mb
Max.
Units
CIN Input Capacitance (A0-A11, BS0, BS1, CS, RAS, CAS, WE, CKE, DQM)
2.5
5.0
3.8
pF
CADD
Address
2.5 5.0 3.8 pF
CCLK
Input Clock (CLK)
2.5 4.0 3.5 pF
COUT
Output Capacitance (DQ0 - DQ15)
4.0 6.5 6.0 pF
REV 1.0
08/2006
5
The Document is a general product description and is subject to change without notice.
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet N2SV6H16FS-6K.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| N2SV6H16FS-6K | SDRAM | Elixir |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |