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N2SV12816FS-75B 데이터시트 PDF




Elixir에서 제조한 전자 부품 N2SV12816FS-75B은 전자 산업 및 응용 분야에서
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부품번호 N2SV12816FS-75B 기능
기능 SDRAM
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N2SV12816FS-75B 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Features
• Fully Synchronous to Positive Clock Edge
• Four Banks controlled by BS0/BS1 (Bank Select)
• Programmable CAS Latency: 2, 3
• Programmable Burst Length: 1, 2, 4, 8, Full page
• Programmable Wrap: Sequential or Interleave
• Burst Read with Single Write Operation
• Automatic and Controlled Precharge Command
N2SV12816FS-6K/75B
N2SV6H16FS-6K/75B
64Mb/128Mb Synchronous DRAM
• Dual Data Mask for byte control (x16)
• Auto Refresh and Self Refresh
• 64ms refresh period (4K cycle)
• JEDEC standard 3.3V Power Supply
• LVTTL compatible
• Package: 54-pin TSOP (II)
Description
The N2SV6H16FS is four-bank Synchronous DRAMs orga-
nized as 1Mbit x 16 I/O x 4 Bank, and N2SV12816FS orga-
nized as 2 Mbit x 16 I/O x 4 Bank. These synchronous
devices achieve high-speed data transfer rates of up to
166MHz by employing a pipeline chip architecture that syn-
chronizes the output data to a system clock.
The device is designed to comply with all JEDEC standards
set for synchronous DRAM products, both electrically and
mechanically. All of the control, address, and data input/out-
put (I/O or DQ) circuits are synchronized with the positive
edge of an externally supplied clock.
RAS, CAS, WE, and CS are pulsed signals which are exam-
ined at the positive edge of each externally applied clock
(CK). Internal chip operating modes are defined by combina-
tions of these signals and a command decoder initiates the
necessary timings for each operation. A fourteen bit address
bus accepts address data in the conventional RAS/CAS mul-
tiplexing style. Twelve row addresses (A0-A11) and two bank
select addresses (BS0, BS1) are strobed with RAS. Eight col-
umn addresses (A0-A8) plus bank select addresses and A10
are strobed with CAS.
Prior to any access operation, the CAS latency, burst length,
and burst sequence must be programmed into the device by
address inputs A0-A7, BS0, BS1 during a mode register set
cycle. In addition, it is possible to program a multiple burst
sequence with single write cycle for write through cache oper-
ation.
Operating the four memory banks in an interleave fashion
allows random access operation to occur at a higher rate
than is possible with standard DRAMs. A sequential and gap-
less data rate of up to 166MHz is possible depending on
burst length, CAS latency, and speed grade of the device.
Simultaneous operation of both decks of a stacked device is
allowed, depending on the operation being done. Auto
Refresh (CBR) and Self Refresh operation are supported.
REV 1.0
08/2006
1
The Document is a general product description and is subject to change without notice.




N2SV12816FS-75B pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
Ordering Information
Organization
4M x 16
8M x 16
Part Number
N2SV6H16FS-6K
N2SV6H16FS-75B
N2SV12816FS-6K
N2SV12816FS-75B
N2SV12816FS-6K/75B
N2SV6H16FS-6K/75B
64Mb/128Mb Synchronous DRAM
Speed Grade
Clock Frequency@CAS Latency
166MHz@CL3
133MHz@CL3
166MHz@CL3
133MHz@CL3
Power
Supply
Package
3.3 V
54-PIN
TSOP II Green
REV 1.0
08/2006
4
The Document is a general product description and is subject to change without notice.

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N2SV12816FS-75B 전자부품, 판매, 대치품
www.DataSheet4U.com
N2SV12816FS-6K/75B
N2SV6H16FS-6K/75B
64Mb/128Mb Synchronous DRAM
Operating, Standby, and Refresh Currents (TA = 0 to +70°C, VDD = 3.3V ±0.3V)
Parameter
Symbol
Test Condition
Operating Current
Precharge Standby Current in
Power Down Mode
Precharge Standby Current in
Non-Power Down Mode
No Operating Current
(Active state: 4 bank)
Operating Current (Burst
Mode)
Auto (CBR) Refresh Current
Self Refresh Current
ICC1
ICC2P
ICC2PS
ICC2N
ICC2NS
ICC3N
ICC3P
ICC4
ICC5
ICC6
1 bank operation
tARcCtiv=et-RPCr(emchina)r,gtCeKco=mmminand cycling
without burst operation
CCKSE=VVIHIL((mmianx) ), tCK = min,
CCKSE=VVIHIL((mmianx) ), tCK = Infinity,
CKE VIH(min), tCK = min,
CS = VIH (min)
CKE VIH(min), tCK = Infinity,
CKE VIH(min), tCK = min,
CS = VIH (min)
CKE VIL(max), tCK = min,
RtCeKad=/
min,
Write
command
cycling,
Multiple banks active, gapless data,
BL = 4
tCK = min, tRC = tRC(min)
CBR command cycling
CKE 0.2V
-6K
(6ns)
140
-75B
(7ns)
Units Notes
100 mA 1, 2, 3
8 8 mA 1
8 8 mA 1
30 30 mA 1, 5
20 20 mA 1, 7
45 45 mA 1, 5
15 15 mA 1, 6
160 120 mA 1, 3, 4
230 210 mA 1
8 8 mA 1
1. Currents given are valid for a single device. The total current for a stacked device depends on the operation being performed
on the other deck.
2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC.
Input signals are changed up to three times during tRC(min).
3. The specified values are obtained with the output open.
4. Input signals are changed once during tCK(min).
5. Input signals are changed once during three clock cycles.
6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ).
7. Input signals are stable.
REV 1.0
08/2006
7
The Document is a general product description and is subject to change without notice.

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