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P1818 데이터시트 PDF




Alliance Semiconductor에서 제조한 전자 부품 P1818은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 P1818 기능
기능 (P1818 - P1822) Low Power Mobile VGA EMI Reduction IC
제조업체 Alliance Semiconductor
로고 Alliance Semiconductor 로고


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P1818 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Production
March 2003
® P1818/19/20/21/22
Low Power Mobile VGA EMI Reduction IC
Features
• FCC approved method of EMI attenuation
• Provides up to 15 dB EMI reduction
• Generates a low EMI spread spectrum clock and a
non-spread reference clock of the input frequency
• Optimized for frequency range from 10 MHz to 160
MHz
P1818: 10 to 20 MHz
P1819: 20 to 40 MHz
P1820: 40 to 80 MHz
P1821: 10 to 40 MHz
P1822: 80 to 160 MHz
• Internal loop filter minimizes external components
and board space
• Selectable spread options: Down Spread and Cen-
ter Spread
• Low inherent cycle-to-cycle jitter
• Eight spread % selections: +/-0.625% to –3.5%
• 3.3V operating voltage
• CMOS/TTL compatible inputs and outputs
• Low power CMOS design
• Supports notebook VGA and other LCD timing
controller applications
• Power down function for mobile application
• Products are available for industrial temperature
range.
• Available in 8-pin SOIC and TSSOP
Product Description
The P18xx is a versatile spread spectrum frequency
modulator designed specifically for a wide range of input
clock frequencies from 10 to 160 MHz (see Input Fre-
quency and Modulation Rate Selections). The P18xx
can generate an EMI reduced clock from crystal,
ceramic resonator, or system clock. The P18xx-A to
P18xx-H offer various combinations of spread options
and percentage deviations (see Spread Deviation Selec-
tions). These combinations include Down Spread,
Center Spread and percentage deviation range from
±0.625% to -3.50%.
The P18xx reduces electromagnetic interference (EMI)
at the clock source, allowing a system wide EMI
reduction for all the down stream clocks and data
dependent signals. The P18xx allows significant system
cost savings by reducing the number of circuit board
layers, ferrite beads, shielding, and other passive
components that are traditionally required to pass EMI
regulations.
The P18xx modulates the output of a single PLL in
order to “spread” the bandwidth of a synthesized clock,
thereby decreasing the peak amplitudes of its
harmonics. This results in significantly lower system
EMI compared to the typical narrow band signal
produced by oscillators and most clock generators.
Lowering EMI by increasing a signal’s bandwidth is
called “spread spectrum clock generation”.
The P18xx uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented by using a proprietary all-digital method.
Applications
The P18xx is targeted toward EMI management for
memory and LVDS interfaces in mobile graphic
chipsets and high-speed digital applications such as
PC peripheral devices, consumer electronics, and
embedded controller systems.
Alliance Semiconductor
2575 Augustine Drive • Santa Clara, CA 95054 • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.




P1818 pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
P1818/19/20/21/22
®
Frequency vs. Deviation (P1818A and P1818H)
Frequency
10 MHz
15 MHz
20 MHz
Pin Description
Deviation in P1818A
SRS = 1
-4.4%
-1.8%
-0.8%
SRS = 0
-3.3%
-1.26%
-0.6%
Deviation in P1818H
D_C = 1
-4.4%
-1.8%
-0.8%
D_C = 0
±2.2%
±0.9%
±0.4%
Pin
number
Name
Type
Description
1 XIN I Connect to externally generated clock signal or crystal.
2 VSS P Ground Connection. Connect to system ground.
3 SRS I Spread Range Select. Digital logic input used to select frequency devi-
ation (see Spread Deviation Selections). This pin has an internal pull-
up resistor.
31 D_C
4 ModOut
5 REF
5/61 FRS
61 PD#
7 VDD
8 XOUT
81 MRS
I Digital logic input used to select Down (LOW) or Center (HIGH) Spread
Options (see Spread Deviation Selections). This pin has an internal
pull-up resistor.
O Spread Spectrum clock output (see Input Frequency and Modulation
Rate Selections and Spread Deviation Selections).
O Non-modulated reference output clock of the input frequency.
I Frequency Range Select. Digital logic input used to select input fre-
quency range (see Input Frequency and Modulation Rate Selections).
This pin has an internal pull-up resistor.
I Power-Down control pin. Pull LOW to enable Power-Down mode. This
pin has an internal pull-up resistor.
P Connect to +3.3V
I Connect to crystal. No connect if externally generated clock signal is
used.
I Modulation Rate Select. Digital logic input used to select Modulation
Rate (see Spread Deviation Selections). This pin has an internal pull-
up resistor.
1. Please refer to Figure 1 for pin assignment.
March 2003
Low Power Mobile VGA EMI Reduction IC
Notice: The information in this document is subject to change without notice.
4 of 8

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P1818 전자부품, 판매, 대치품
www.DataSheet4U.com
P1818/19/20/21/22
®
Mechanical Package Outline (8-Pin SOIC)
P18xxx
LOT NUMBER
YYWW
H
D
Be
A2 A
A1
Inches
Millimeters
Symbol
C Min Nor Max Min Nor Max
L A 0.057 0.064 0.071 1.45 1.63 1.80
A1 0.004 0.007 0.010 0.10 0.18 0.25
E A2 0.053 0.061 0.069 1.35 1.55 1.75
B 0.012 0.016 0.020 0.31 0.41 0.51
C 0.004 0.006 0.01 0.10 0.15 0.25
a D 0.186 0.194 0.202 4.72 4.92 5.12
E 0.148 0.156 0.164 3.75 3.95 4.15
e 0.050 BSC
1.27 BSC
H 0.224 0.236 0.248 5.70 6.00 6.30
L 0.012 0.020 0.028 0.30 0.50 0.70
a 0° 5° 8° 0° 5° 8°
Note: Controlling dimensions are millimeters.
SOIC: 0.074 grams unit weight.
Mechanical Package Outline (8-Pin TSSOP)
H
D
Be
A2 A
A1
Inches
Millimeters
Symbol
C Min Nor Max Min Nor Max
L A – – 0.047 – – 1.10
A1 0.002 – 0.006 0.05 – 0.15
E A2 0.031 0.039 0.041 0.80 1.00 1.05
B 0.007 – 0.012 0.19 – 0.30
C 0.004 – 0.008 0.09 – 0.20
a D 0.114 0.118 0.122 2.90 3.00 3.10
E 0.169 0.173 0.177 4.30 4.40 4.50
e 0.026 BSC
0.65 BSC
H 0.244 0.252 0.260 6.20 6.40 6.60
L 0.018 0.024 0.030 0.45 0.60 0.75
a 0° – 8° 0° – 8°
Note: Controlling dimensions are millimeters.
TSSOP: 0.034 grams unit weight.
March 2003
Low Power Mobile VGA EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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