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PDF STAC9721 Data sheet ( Hoja de datos )
| Número de pieza | STAC9721 | |
| Descripción | (STAC9721 / STAC9723) Stereo AC 97 Codec | |
| Fabricantes | ETC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de STAC9721 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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SigmaTel, Inc.
Integrating Mixed-Signal Solutions
DATA SHEET
STAC9721/23
Stereo AC'97 Codec
With Multi-Codec Option
GENERAL DESCRIPTION:
SigmaTel’s STAC9721/23 is a general-purpose 18-bit stereo, full duplex, audio codec that conforms to
the analog component specification of AC'97 (Audio Codec 97 Component Specification Rev. 2.1). The
STAC9721/23 incorporates SigmaTel’s proprietary Sigma-Delta technology to achieve a DAC SNR in
excess of 95dB. The DACs, ADCs, and mixer are integrated with analog I/Os, which include four analog
line-level stereo inputs, two analog line-level mono inputs, two stereo outputs, and one mono output
channel. Also included are SigmaTel’s 3D stereo enhancement (SS3D), and an extra true line-level out
for headphones or speaker amplifiers. The STAC9721/23 may be used as a secondary codec, with the
STAC9700/04/07/44/45 or a 4-channel STAC9708 as the primary, in multiple codec configurations
conforming to the AC'97 Rev. 2.1 specification. This configuration can provide up to six-channel output,
providing AC-3 playback for DVD applications. The STAC9721/23 communicates via the five-wire AC-
Link interface with any AC-Link capable controller or advanced core logic chip-set. Packaged in an
AC'97 compliant 48-pin TQFP, the STAC9721/23 can be placed on motherboards, daughter boards, add-
on cards or AMR/MDC cards.
FEATURES:
• High performance Σ∆ technology
• Energy saving power down modes
• 18-bit full duplex stereo ADC, DACs
• AC-Link protocol compliance
• 3.3V Multiple power supply options
• Pin compatible with the STAC9700/44/45
• SigmaTel Surround (SS3D) Stereo Enhancement
• EAPD – External Amplifier Power Down Control
• Multi-Codec option (Intel AC'97 rev 2.1)
• Six analog line-level inputs
• 48-pin TQFP
• LINE-to-LINE SNR 102dB
• The STAC9723 is tested at +3.3V
ORDERING INFORMATION:
PART
NUMBER
STAC9721T
STAC9723T
PACKAGE
48-pin TQFP 7mm x7mm x 1.4mm
48-pin TQFP 7mmx7mm x 1.4mm
TEMPERATURE
RANGE
0o C to +70o C
0o C to +70o C
SUPPLY RANGE
DVdd = 3.3V or 5V, AVdd = 5V
DVdd = 3.3V, AVdd = 3.3V
SigmaTel reserves the right to change specifications without notice
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SigmaTel, Inc.
Data Sheet
STAC9721
AC-link
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
RESET
Power
Management
Digital
Interface
Registers
64 x 16 bits
4 stereo
sources
PCM out DACs
48Kss
DAC
DAC
PCM in ADCs
ADC
ADC
48Kss
2 mono sources
mono
stereo
MIXER
Analog mixing
and
Gain control
LNLVL_OUT
LINE_OUT
MONO_OUT
Mic
MIC1
M
Boost
U
0/20 dB X MIC2
Figure 2. STAC9721/23 Block Diagram
The STAC9721/23 block diagram is illustrated above. It performs fixed 48K sample rate D-A & A-D
conversion, mixing, and analog processing. The digital interface communicates with the AC'97 controller
via the five wire AC-Link and contains the 64 word by 16-bit registers. Two, fixed 48Ks/s DAC’s
support two stereo PCM-out channels. The digital mix of all software sources, including the internal
synthesizer and any other digital sources, is performed in the digital controller. The Mixer block mixes
the PCM_OUT with any analog sources, then outputs to LINE_OUT and LNLVL_OUT. The
MONO_OUT delivers either mic only or a mono mix of sources from the mixer. The two fixed 48Ks/s
ADC’s take any mix of mono or stereo sources and convert it to a stereo PCM-in signal. All ADC's and
DAC's operate at 18-bit resolution.
The STAC9721/23 is designed primarily to support stereo, 2-speaker audio. However, true AC-3
playback can be achieved for 6-speaker applications by taking advantage of the multi-codec option in the
STAC9721/23. Using this option with a STAC9704/07/21/23 or the 4-channel STAC9708 as the primary
codec, and the STAC9721/23 as the secondary codec, 6-channel output can be achieved in an AC'97
architecture. Also, the STAC9721/23 provides for a stereo enhancement feature, SigmaTel Surround 3D
or SS3D. SS3D provides the listener with several options to expand the soundstage beyond the normal 2-
speaker arrangement.
Together, with the logic component (controller or advanced core logic chip-set) of AC'97, the
STAC9721/23 can be SoundBlaster and Windows Sound System compatible. SoundBlaster is a
registered trademark of Creative Labs. Windows is a registered trademark of Microsoft Corporation.
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SigmaTel, Inc.
Data Sheet
STAC9721
3. DIGITAL INTERFACE
3.1 AC-Link Digital Serial Interface Protocol
The STAC9721/23 communicates to the AC'97 controller via a 5-pin digital serial AC-Link interface,
which is a bi-directional, fixed rate, serial PCM digital stream. All digital audio streams, commands and
status information are communicated over this point-to-point serial interconnect. The AC-Link handles
multiple inputs, and output audio streams, as well as control register accesses using a time division
multiplexed (TDM) scheme. The AC'97 controller synchronizes all AC-Link data transaction. The
following data streams are available on the STAC9721/23:
PCM Playback
4 output slots
4 Channel composite PCM output stream
PCM Record data
2 input slots
2 Channel composite PCM input stream
Control
2 output slots
Control register write port
Status
2 input slots
Control register read port
Synchronization of all AC-Link data transactions is handled by the AC'97 controller. The STAC9721/23
drives the serial bit clock onto AC-Link. The AC'97 controller then qualifies with a synchronization
signal to construct audio frames.
SYNC, fixed at 48 kHz, is derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed at
12.288 MHz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming
time slots. AC-Link serial data is transitioned on each rising edge of BIT_CLK. The receiver of AC-
Link data, STAC9721/23 for outgoing data and AC'97 controller for incoming data, samples each serial
bit on the falling edges of BIT_CLK.
The AC-Link protocol provides for a special 16-bit (13-bits defined, with 3 reserved trailing bit positions)
time slot (Slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current
audio frame. A “1” in a given bit position of slot 0 indicates that the corresponding time slot within the
current audio frame has been assigned to a data stream, and contains valid data. If a slot is “tagged”
invalid, it is the responsibility of the source of the data (STAC9721/23 for the input stream, AC'97
controller for the output stream) to stuff all bit positions with 0’s during that slot’s active time.
SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The
portion of the audio frame where SYNC is high is defined as the “Tag Phase”. The remainder of the
audio frame where SYNC is low is defined as the “Data Phase”.
Additionally, for power savings, all clock, sync, and data signals can be halted.
11 04/07/00
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet STAC9721.PDF ] | |
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