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STAC9752 데이터시트 PDF




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부품번호 STAC9752 기능
기능 (STAC9752 / STAC9753) TWO-CHANNEL AC97 2.3 CODECS
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STAC9752 데이터시트, 핀배열, 회로
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DATASHEET
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE STAC9752/9753
DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
Description
IDT's STAC9752/9753 are general purpose 20-bit, full
duplex, audio CODECs conforming to the analog
component specification of AC'97 (Audio CODEC 97
Component Specification Rev. 2.3). The STAC9752/9753
incorporate IDT's proprietary Σ∆ technology to achieve a
DAC SNR in excess of 90dB. The DACs, ADCs and mixer
are integrated with analog I/Os, which include four analog
line-level stereo inputs, two analog line-level mono inputs,
two stereo outputs, and one mono output channel. The
STAC9752/9753 include digital output capability for support
of modern PC systems with an output that supports the
SPDIF format. The STAC9752/9753 are standard
2-channel stereo CODECs. With IDT’s headphone
capability, headphones can be driven without an external
amplifier. The STAC9752/9753 may be used as a
secondary or tertiary CODECs, with STAC9700/21/44/56/
08/84/50/66 as the primary, in a multiple CODEC
configuration conforming to the AC'97 Rev. 2.3
specification. This configuration can provide the true
six-channel, AC-3 playback required for DVD applications.
The STAC9752/9753 communicate via the five AC-Link
lines to any digital component of AC'97, providing flexibility
in the audio system design. Packaged in an AC'97
compliant 48-pin TQFP, the STAC9752/9753 can be placed
on the motherboard, daughter boards, PCI, AMR, CNR,
MDC or ACR cards.
Features
High performance Σ∆ technology
AC’97 Rev 2.3 compliant
20-bit full duplex stereo ADCs, DACs
Independent sample rates for ADCs & DACs
5-wire AC-Link protocol compliance
20-bit SPDIF Output
Internal Jack Sensing on Headphone and Line_Out
Internal Microphone Input Sensing
Digital PC Beep Option
Extended AC’97 2.3 Paging Registers
Adjustable VREF amplifier
Digital-ready status
General purpose I/Os
Crystal Elimination Circuit
Headphone drive capability (50 mW)
0dB, 10dB, 20dB, and 30dB microphone boost
capability
+3.3 V (STAC9753) and +5 V (STAC9752) analog
power supply options
Pin compatible with the STAC9700, STAC9721,
STAC9756
100% pin compatible with STAC9750 and
STAC9766
IDT Surround (SS3D) Stereo Enhancement
Energy saving dynamic power modes
Multi-CODEC option (Intel AC'97 rev 2.3)
Six analog line-level inputs
90dB SNR Line to Line
SNR > 89dB through Mixer and DAC
IDT™
1 STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
V 3.3 101006




STAC9752 pdf, 반도체, 판매, 대치품
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
8.2.6. GPIO Pin Polarity/Type Register (4Eh) ............................................................................. 66
8.2.7. GPIO Pin Sticky Register (50h) ......................................................................................... 66
8.2.8. GPIO Pin Mask Register (52h) .......................................................................................... 67
8.2.9. GPIO Pin Status Register (54h) ........................................................................................ 67
8.3. Extended CODEC Registers Page Structure Definition .................................................................. 68
8.3.1. Extended Registers Page 00 ............................................................................................. 68
8.3.2. Extended Registers Page 01 ............................................................................................. 68
8.3.3. Extended Registers Page 02, 03 ....................................................................................... 68
8.4. STAC9752/9753 Paging Registers ................................................................................................. 69
8.4.1. CODEC Class/Rev (60h Page 01h ) ............................................................................... 69
8.4.2. PCI SVID (62h Page 01h) ............................................................................................... 70
8.4.3. PCI SSID (64h Page 01h) ............................................................................................... 70
8.4.4. Function Select (66h Page 01h) ...................................................................................... 71
8.4.5. Function Information (68h Page 01h ) .............................................................................. 72
8.4.6. Digital Audio Control (6Ah, Page 00h) ............................................................................... 73
8.4.7. Sense Details (6Ah Page 01h) ........................................................................................ 74
8.4.8. Revision Code (6Ch) ........................................................................................................ 76
8.4.9. Analog Special (6Eh) ......................................................................................................... 76
8.4.10. Analog Current Adjust (72h) ............................................................................................ 77
8.4.11. EAPD Access Register (74h) .......................................................................................... 77
8.4.12. High Pass Filter Bypass (78h) ........................................................................................ 78
8.5. Vendor ID1 and ID2 (Index 7Ch and 7Eh) ...................................................................................... 79
8.5.1. Vendor ID1 (7Ch) ............................................................................................................. 79
8.5.2. Vendor ID2 (7Eh) ............................................................................................................... 79
9. LOW POWER MODES ...........................................................................................................80
10. MULTIPLE CODEC SUPPORT ............................................................................................82
10.1. Primary/Secondary CODEC Selection .......................................................................................... 82
10.1.1. Primary CODEC Operation ............................................................................................ 82
10.1.2. Secondary CODEC Operation ........................................................................................ 82
10.2. Secondary CODEC Register Access Definitions .......................................................................... 83
11. TESTABILITY ........................................................................................................................84
11.0.1. ATE Test Mode ................................................................................................................ 84
12. PIN DESCRIPTION ................................................................................................................85
12.1. Digital I/O ...................................................................................................................................... 86
12.2. Analog I/O .................................................................................................................................... 87
12.3. Filter/References .......................................................................................................................... 88
12.4. Power and Ground Signals .......................................................................................................... 88
13. ORDERING INFORMATION ..................................................................................................89
14. PACKAGE DRAWING ...........................................................................................................89
15. 48-PIN LQFP SOLDER REFLOW PROFILE .........................................................................90
15.1. Standard Reflow Profile Data ........................................................................................................ 90
15.2. Pb Free Process - Package Classification Reflow Temperatures ................................................. 91
16. APPENDIX A: PROGRAMMING REGISTERS .....................................................................92
17. REVISION HISTORY .............................................................................................................94
IDT™
4 STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
REV 3.3 1206

4페이지










STAC9752 전자부품, 판매, 대치품
STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
1. PRODUCT BRIEF
1.1.
Description
IDT's STAC9752/9753 are general purpose 20-bit, full duplex, audio CODECs conforming to the
analog component specification of AC'97 (Audio CODEC 97 Component Specification Rev. 2.3).
The STAC9752/9753 incorporate IDT's proprietary Σ∆ technology to achieve a DAC SNR in excess
of 90dB. The DACs, ADCs and mixer are integrated with analog I/Os, which include four analog
line-level stereo inputs, two analog line-level mono inputs, two stereo outputs, and one mono output
channel. The STAC9752/9753 include digital output capability for support of modern PC systems
with an output that supports the SPDIF format. The STAC9752/9753 are standard 2-channel stereo
CODECs. With IDT’s headphone capability, headphones can be driven without an external amplifier.
The STAC9752/9753 may be used as a secondary or tertiary CODECs, with STAC9700/21/44/56/
08/84/50/66 as the primary, in a multiple CODEC configuration conforming to the AC'97 Rev. 2.3
specification. This configuration can provide the true six-channel, AC-3 playback required for DVD
applications. The STAC9752/9753 communicate via the five AC-Link lines to any digital component
of AC'97, providing flexibility in the audio system design. Packaged in an AC'97 compliant 48-pin
TQFP, the STAC9752/9753 can be placed on the motherboard, daughter boards, PCI, AMR, CNR,
MDC or ACR cards.
The STAC9752/9753 block diagram is illustrated in Figure 1. The STAC9752/9753 provides variable
sample rate Digital-to-Analog (DA) and Analog-to-Digital (AD) conversion, mixing, and analog pro-
cessing. Supported audio sample rates include 48 KHz, 44.1 KHz, 32 KHz, 22.05 KHz, 16 KHz,
11.025 KHz, and 8 KHz; additional rates are supported in the STAC9752/9753 soft audio drivers. All
ADCs and DACs operate at 20-bit resolution.
Two 20-bit DACs convert the digital stereo PCM_OUT content to audio. The MIXER block combines
the PCM_OUT with any analog sources, to drive the LINE_OUT and HP_OUT outputs. The
MONO_OUT delivers either microphone only, or a mono mix of sources from the MIXER. The stereo
variable-sample-rate 20-bit ADCs provide record capability for any mix of mono or stereo sources,
and deliver a digital stereo PCM-in signal back to the AC-Link. The microphone input and mono mix
input can be recorded simultaneously, thus allowing for an all digital output in support of the digital
ready initiative. For a digital ready record path, the microphone is connected to the left channel ADC
while the mono output of the stereo mixer is connected to right channel ADC.
The STAC9752/9753 include jack sensing on the Headphone and Line_Out. The STAC9752/9753
jack sense can detect the presence of devices on the Headphone and Line Outputs and on both
Microphone inputs. With proprietary IDT current and impedance-sensing techniques, the impedance
load on the Headphone and Line Outputs can also be detected. The GPIOs on the STAC9752/9753
remain available for advanced configurations.
The STAC9752/9753 implementation of jack sense uses the Extended Paging Registers defined by
the AC'97 2.3 Specification. This allows for additional registry space to hold the identification infor-
mation about the CODEC, the jack sensing details and results, and the external surroundings of the
CODEC. The information within the Extended Paging Registers will allow for the automatic configu-
ration of the audio subsystem without end-user intervention. For example, the BIOS can populate
the Extended Paging Registers with valuable information for both the audio driver and the operating
system such as gain and attenuation stages, input population and input phase. With this input infor-
mation, the IDT driver will automatically provide to the Volume Control Panel only the volume sliders
that are implemented in the system, thus improving the end-user's experience with the PC.
The information in the Extended Paging Registers will also allow for automatic configuration of
microphone inputs, the ability to switch between SPDIF and analog outputs, the routing of the mas-
IDT™
7 STAC9752/9753
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH HEADPHONE DRIVE, SPDIF OUTPUT MICROPHONE & JACK SENSING
REV 3.3 1206

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