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PDF STAC9752A Data sheet ( Hoja de datos )

Número de pieza STAC9752A
Descripción (STAC9752A / STAC9753A) AC97 2.3 CODECS
Fabricantes IDT　
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DATASHEET
AC’97 2.3 CODECS WITH STEREO
MICROPHONE & UNIVERSAL JACK
FEATURES
• High Performance Σ∆ Technology
• AC’97 Rev 2.3 Complaint
• 20-bit Full Duplex Stereo ADC & DACs
• Independent Sample Rates for ADC & DACs
• 5-Wire AC-Link Protocol Compliance
• 20-Bit SPDIF Output
• Universal Jacks™
• Full Stereo Microphone Pre-Amp
• Internal Jack Sensing on Headphone & Line_Out
• Internal Microphone Input Sensing
• Digital PC Beep Option
• Extended AC’97 2.3 Paging Registers
• General Purpose I/Os and Crystal Elimination
Circuit
• Headphone Drive Capability (50 mW per channel)
• Switchable Headphone Out (pins 39/41 or 35/36)
• 0dB, 10dB, 20dB and 30dB Microphone Boost
Capability
• +3.3 V (STAC9753A) and +5 V (STAC9752A) Analog
Power Supply Options
• Pin Compatible with STAC9750/52/66
KEY SPECIFICATIONS
• Analog LINE_OUT SNR: 94dB
• Digital DAC SNR: 92dB
• Digital ADC SNR: 85dB
• Full-scale Total Harmonic Distortion: 0.002%
• Crosstalk Between Input Channels: -70dB
• Spurious Tone Rejection: 100dB
• Stereo Microphone Input
RELATED MATERIALS
• Data Sheet
STAC9752A/9753A
• Reference Designs
DESCRIPTION
IDT's STAC9752A/9753A are general purpose 20-bit, full
duplex, audio CODECs conforming to the analog compo-
nent specification of AC'97 (Audio CODEC 97 Component
Specification Rev. 2.3). The STAC9752A/9753A incorpo-
rates IDT's proprietary Σ∆ technology.
The AC’97 CODEC is designed to achieve a DAC SNR in
excess of 94dB. The DACs, ADCs, and mixer are inte-
grated with analog I/Os, which include four analog
line-level stereo inputs, two analog line-level mono inputs,
two stereo outputs, and one mono output channel.
The STAC9752A/9753A includes digital input/output capa-
bility for support of modern PC systems, with an output that
supports the SPDIF format. The STAC9752A/9753A is a
standard 2-channel stereo CODEC. With IDT’s headphone
drive capability, headphones can be driven with without an
external amplifier.
The STAC9752A/9753A may be used as a secondary
CODEC, with the STAC9700/21/56/08/84/50/52 as the pri-
mary, in a multiple CODEC configuration conforming to the
AC'97 Rev. 2.3 specification. This configuration can pro-
vide the true six-channel, AC-3 playback required for DVD
applications.
The STAC9752A/9753A communicates via the five-wire
AC-Link to any digital component of AC'97, providing flexi-
bility in the audio system design.
Packaged in an AC'97 compliant 48-pin TQFP, the
STAC9752A/9753A can be placed on a motherboard,
daughter boards, PCI, AMR, CNR, MDC or ACR cards.
The STAC9752A/9753A provides variable sample rate Dig-
ital-to-Analog (DA) and Analog-to-Digital (AD) conversion,
mixing, and analog processing.
Supported audio sample rates include 48KHz, 44.1KHz,
32KHz, 22.05KHz, 16KHz, 11.025KHz, and 8 KHz; addi-
tional rates are supported in the STAC9752A/9753A soft
audio drivers. All ADCs and DACs operate at 20-bit resolu-
IDT™
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
1
STAC9752A/9753A
V 1.5 1206

1 page




STAC9752A pdf
STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
LIST OF TABLES
Table 1. Clock mode configuration ................................................................................................................ 17
Table 2. Common Clocks and Sources ......................................................................................................... 18
Table 3. Recommended CODEC ID strapping .............................................................................................. 27
Table 4. AC-Link Output Slots (transmitted from the Controller) ................................................................... 31
Table 5. The AC-Link Input Slots (transmitted from the CODEC) .................................................................32
Table 6. VRA Behavior .................................................................................................................................. 33
Table 7. Output Slot 0 Bit Definitions ............................................................................................................. 36
Table 8. Command Address Port Bit Assignments ........................................................................................ 37
Table 9. Status Address Port Bit Assignments .............................................................................................. 40
Table 10. Status Data Port Bit Assignments .................................................................................................. 41
Table 11. Primary CODEC Addressing: Slot 0 Tag Bits ................................................................................ 42
Table 12. Secondary CODEC Addressing: Slot 0 tag bits ............................................................................. 43
Table 13. AC-Link Output Slots Dedicated To CODEC ................................................................................. 43
Table 14. AC-Link Output Slots Dedicated To Audio ..................................................................................... 44
Table 15. AC-Link Input Slots Dedicated To Audio ....................................................................................... 44
Table 16. Audio Interrupt Slot Definitions ...................................................................................................... 45
Table 17. Digital PC Beep Examples ............................................................................................................. 49
Table 18. Programming Registers ................................................................................................................. 50
Table 19. Extended Audio ID Register Functions .......................................................................................... 64
Table 20. AMAP compliant ............................................................................................................................ 66
Table 21. Hardware Supported Sample Rates .............................................................................................. 67
Table 22. Supported Jack and Mic Sense Functions .................................................................................... 75
Table 23. Reg 68h Default Values ................................................................................................................. 77
Table 24. Gain or Attenuation Examples ....................................................................................................... 77
Table 25. Register 68h/Page 01h Bit Overview ............................................................................................. 77
Table 26. Sensed Bits (Outputs) ................................................................................................................... 79
Table 27. Sensed Bits (Inputs) ...................................................................................................................... 79
Table 28. Low Power Modes ......................................................................................................................... 85
Table 29. CODEC ID Selection .....................................................................................................................87
Table 30. Secondary CODEC Register Access Slot 0 Bit Definitions ...........................................................88
Table 31. Test Mode Activation .....................................................................................................................89
Table 32. ATE Test Mode Operation ............................................................................................................. 89
Table 33. STAC9752A/9753A 48 Pin LQFP Pin List ..................................................................................... 91
Table 34. STAC9752A/9753A 32 Pad QFN Pin List ...................................................................................... 93
Table 35. STAC9752A/9753A Digital Connection Signals ............................................................................ 93
Table 36. STAC9752A/9753A Analog Connection Signals ........................................................................... 94
Table 37. STAC9752A/9753A Filtering and Voltage References .................................................................. 95
Table 38. STAC9752A/9753A Power and Ground Signals ........................................................................... 96
Table 39. STAC9752A/9753A No Connects .................................................................................................. 96
IDT™
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
5
STAC9752A/9753A
V 1.5 1206

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STAC9752A arduino
STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
PC AUDIO
2.1.3.
Power Consumption
Parameter
Digital Supply Current
+ 3.3 V Digital
Analog Supply Current
+ 5 V Analog
+ 3.3 V Analog
Power Down Status
PR0 Supply Current
PR1 Supply Current
PR2 Supply Current
PR3 Supply Current
PR4 Supply Current
PR5 Supply Current
PR6 Supply Current
Min Typ Max Unit
- 35 - mA
- 80 - mA
- 70 - mA
-
TBD
- mA
-
TBD
- mA
-
TBD
- mA
-
TBD
- mA
-
TBD
- mA
-
TBD
- mA
-
TBD
- mA
2.1.4.
AC-Link Static Digital Specifications
(Tambient = 25 ºC, DVdd = 3.3 V ± 5%, AVss = DVss = 0 V; 50 pF external load)
Parameter
Input Voltage Range
Low level input range
High level input voltage
High level output voltage
Low level output voltage
Input Leakage Current (AC-Link inputs)
Output Leakage Current (Hi-Z AC-Link outputs)
Output buffer drive current
Symbol
Vin
Vil
Vih
Voh
Vol
-
-
-
Min
-0.30
-
0.65 x DVdd
0.90 x DVdd
-
-10
-10
-
Typ
-
-
-
-
-
-
-
4
Max
DVdd + 0.30
0.35 x DVdd
-
-
0.1 x DVdd
10
10
-
Unit
V
V
V
V
V
µA
µA
mA
IDT™
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
11
STAC9752A/9753A
V 1.5 1206

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