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Número de pieza | MPC562 | |
Descripción | (MPC562 / MPC563 / MPC564) RISC MCU Including Peripheral Pin Multiplexing with Flash and Code Compression Options | |
Fabricantes | Motorola Semiconductors | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de MPC562 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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SEMICONDUCTOR
PRODUCT BRIEF
MPC561PB/D
Rev. 1, December 2001
MPC561/MPC562
MPC563/MPC564
Product Brief
MPC561/MPC562 / MPC563/MPC564 RISC MCU
Including Peripheral Pin Multiplexing with
Flash and Code Compression Options
Features
The MPC561/MPC562 / MPC563/MPC564 are members of the Motorola MPC500 RISC Microcontroller
family. As shown in the block diagram, they are composed of:
• High performance CPU system
— High performance core
• Single issue integer core
• Compatible with PowerPC instruction set architecture
• Precise exception model
• Floating point
• Extensive system development support
— On-chip watchpoints and breakpoints
— Program flow tracking
— Background debug mode (BDM)
— IEEE-ISTO Nexus 5001-1999 Class 3 Debug Interface
— MPC500 system interface (USIU, BBC, L2U)
— Fully static design
— Four major power saving modes
• On, doze, sleep, deep-sleep and power-down
— 32-Kbyte static RAM (CALRAM)
— 512-Kbyte flash (UC3F) on MPC563/MPC564
— General-purpose I/O support
• On address (24) and data (32) pins
• 16 GPIO in MIOS14
• Many peripheral pins can be used as GPIO when not used as primary functions
• 2.6-V outputs on external bus pins
• PPM (peripheral pin multiplexing with parallel-to-serial driver) module
• Available in package or die
— Plastic ball grid array (PBGA) packaging
Key Feature Details
MPC500 System Interface (USIU)
• System configuration and protection features:
— Periodic-interrupt timer
— Bus monitor
— Software watchdog timer
— Real-time clock (RTC)
This document contains information on a new product. Specifications and
information herein are subject to change without notice.
© MOTOROLA 2001, All Rights Reserved
1 page MPC561/MPC562 / MPC563/MPC564 Optional Features
The following are optional features of the MPC561/MPC562 / MPC563/MPC564:
• 56-MHz operation (40 MHz is default)
• Code compression supported on the MPC562 and the MPC564
— Compression reduces instruction memory requirements by 40-50%
— Compression optimized for automotive (non-cached) applications
• 512 Kbytes flash (available on the MPC563/MPC564 only)
— Single array
— Page mode read
— Block (64 Kbytes) erasable
— External 4.75- to 5.25-V VFLASH program, erase, and read power supply
JTAG
MPC5xx
Core
+
FP
Burst
Buffer
Controller
512 Kbytes
Flash
(on MPC563/
MPC564 only)
READI
U-BUS
L-BUS
32-Kbyte CALRAM
28-Kbyte
SRAM
(No Overlay)
4-Kbyte Overlay
L2U
Int.
E-BUS
USIU
QADC64 QADC64 QSMCM
PPM
UIMB
I/F
IMB3
TPU3
8-Kbyte
DPTRAM
TPU3
Tou Tou
CAN CAN
Tou
CAN
MIOS14
Figure 1 MPC561/MPC562 / MPC563/MPC564 Block Diagram
MPC561/MPC563
PRODUCT BRIEF
MOTOROLA
5
5 Page MPC561/MPC563
PRODUCT BRIEF
MOTOROLA
11
11 Page |
Páginas | Total 12 Páginas | |
PDF Descargar | [ Datasheet MPC562.PDF ] |
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