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4014BT PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 4014BT
기능 HEF4014B
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4014BT 데이터시트, 핀배열, 회로
HEF4014B
8-bit static shift register
Rev. 9 — 21 March 2016
Product data sheet
1. General description
The HEF4014B is a fully synchronous edge-triggered 8-bit static shift register with eight
synchronous parallel inputs (D0 to D7), a synchronous serial data input (DS), a
synchronous parallel enable input (PE), a LOW-to-HIGH edge-triggered clock input (CP)
and buffered parallel outputs from the last three stages (Q5 to Q7).
Operation is synchronous and the device is edge-triggered on the LOW-to-HIGH
transition of CP. Each register stage is of a D-type master-slave flip-flop type. When PE is
HIGH, data is loaded into the register from D0 to D7 on the LOW-to-HIGH transition of CP.
When PE is LOW, data is shifted to the first position from DS, and all the data in the
register is shifted one position to the right on the LOW-to-HIGH transition of CP. The clock
input’s Schmitt trigger action makes it highly tolerant of slower clock rise and fall times.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits
Tolerant of slow clock rise and fall times
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Applications
Parallel-to-serial converter
Serial data queueing
General purpose register
4. Ordering information
Table 1. Ordering information
All types operate from 40 C to +85 C
Type number Package
Name Description
HEF4014BT
SO16
plastic small outline package; 16 leads; body width 3.9 mm
Version
SOT109-1




4014BT pdf, 반도체, 판매, 대치품
NXP Semiconductors
HEF4014B
8-bit static shift register
7. Functional description
Table 3. Function table[1]
Number of clock
Inputs
Outputs
transitions CP DS PE Q5
Serial operation
1 1D L X
2 2D L X
3 3D L X
6 X L 1D
7 X L 2D
8 X L 3D
X X no change
Parallel operation
1 X H D5
X X no change
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; nD = HIGH or LOW;
= LOW-to-HIGH clock transition; = HIGH-to-LOW clock transition;
8. Limiting values
Q6
X
X
X
X
1D
2D
no change
D6
no change
Q7
X
X
X
X
X
1D
no change
D7
no change
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
VDD
IIK
VI
IOK
II/O
IDD
Tstg
Tamb
Ptot
supply voltage
input clamping current
input voltage
output clamping current
input/output current
supply current
storage temperature
ambient temperature
total power dissipation
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
Tamb = 40 C to +85 C
SO16 package
P power dissipation
per output
[1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
[1]
Min
0.5
-
0.5
-
-
-
65
40
-
-
Max
+18
10
VDD + 0.5
10
10
50
+150
+85
Unit
V
mA
V
mA
mA
mA
C
C
500 mW
100 mW
HEF4014B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 21 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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4014BT 전자부품, 판매, 대치품
NXP Semiconductors
HEF4014B
8-bit static shift register
Table 8. Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol Parameter
VDD Typical formula for PD (W)
Where:
PD
dynamic power 5 V
PD = 900 fi + (fo CL) VDD2
fi = input frequency in MHz;
dissipation
10 V
PD = 4300 fi + (fo CL) VDD2
fo = output frequency in MHz;
15 V
PD = 12000 fi + (fo CL) VDD2
CL = output load capacitance in pF;
VDD = supply voltage in V;
(CL fo) = sum of the outputs.
12. Waveforms
9,
&3LQSXW
966
92+
4QRXWSXW
92/
90
W3+/

90

WW
Measurement points are given in Table 9.
Fig 4. CP to Qn propagation delays and output transition times
W3/+
WW
DDM
9,
&3LQSXW
966
9,
'LQSXW
966
9,
3(LQSXW
966
9,
'6LQSXW
966

WVX WK
 
WVX WK
 

W:

WU
IFON PD[

WI
WVX

WVX
WK

WK
 
DDH
Fig 5.
The shaded areas indicate where change is permitted for predictable output performance.
Set-up and hold times are shown as positive values but may be specified as negative values.
Measurement points are given in Table 9.
Minimum clock pulse width, and set-up and hold times for PE to CP, DS to CP, and D to CP
HEF4014B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 21 March 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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