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PDF AOZ1012D Data sheet ( Hoja de datos )
| Número de pieza | AOZ1012D | |
| Descripción | 3A Simple Buck Regulator | |
| Fabricantes | Alpha & Omega Semiconductors | |
| Logotipo |  |
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EZBuck™ 3A Simple Buck Regulator
April 2006
General Description
The AOZ1012D is a high efficiency, simple to use, 3A buck
regulator. The AOZ1012D works from a 4.5V to 16V input
voltage range, and provides up to 3A of continuous output
current with an output voltage adjustable down to 0.8V.
The AOZ1012D comes in 4X5 DFN-8 packages and is rated
over a -40°C to +85°C ambient temperature range.
Features
• 4.5V to 16V operating input voltage
range
• 50 m Ω internal PFET switch for high
efficiency: up to 95%
• Internal Schottky Diode
• Internal soft start
• Output voltage adjustable to 0.8V
• 3A continuous output current
• Fixed 500kHz PWM operation
• Cycle-by-cycle current limit
• Short-circuit protection
• Thermal shutdown
• Small size DFN-8 packages
Applications
• Point of load dc/dc conversion
• PCIe graphics cards
• Set top boxes
• DVD drives and HDD
• LCD panels
• Cable modems
• Telecom/Networking/Datacom
equipment
Typical Application
VIN
From uPC
RC
CC
C1
22uF
VIN
EN
AOZ1012D LX
COMP
GND
FB
L1 3.3uH
R1
R2
VOUT
+3.3V Output
@3A
C2
47uF
April 2006
Figure 1. 3.3V/3A Buck Down Regulator
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Typical Performance Characteristics
Circuit of figure 1. TA = 25°C, VIN = VEN = 12V, VOUT = 3.3V unless otherwise specified.
Light load (DCM) operation
Vin
ripple
0.1V/div
Full load (CCM) operation
Vo
ripple
20mV/div
Iin
2A/div
1us/div
Start up to full load
VLX
10V/div
Vin
5V/div
1us/div
Full load to turn off
Vo
1V/div
Iin
2A/div
1ms/div
50% to 100% Load transient
1ms/div
Light load to turn off
Vin
ripple
0.1V/div
Vo
ripple
20mV/div
Iin
2A/div
VLX
10V/div
Vin
5V/div
Vo
1V/div
Iin
2A/div
100us/div
Vo
Ripple
0.1V/div
Io
2A/div
1s/div
Vin
5V/div
Vo
1V/div
Iin
2A/div
April 2006
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where CO is output capacitor value and ESRCO is the
Equivalent Series Resistor of output capacitor.
When low ESR ceramic capacitor is used as output
capacitor, the impedance of the capacitor at the
switching frequency dominates. Output ripple is mainly
caused by capacitor value and inductor ripple current.
The output ripple voltage calculation can be simplified
to:
∆VO
=
∆I L
×
8×
1
f × CO
If the impedance of ESR at switching frequency
dominates, the output ripple voltage is mainly decided
by capacitor ESR and inductor ripple current. The
output ripple voltage calculation can be further
simplified to:
∆VO = ∆I L × ESRCO
For lower output ripple voltage across the entire
operating temperature range, X5R or X7R dielectric type
of ceramic, or other low ESR tantalum are
recommended to be used as output capacitors.
In a buck converter, output capacitor current is
continuous. The RMS current of output capacitor is
decided by the peak to peak inductor ripple current. It
can be calculated by:
I CO _ RMS
=
∆I L
12
Usually, the ripple current rating of the output capacitor
is a smaller issue because of the low current stress.
When the buck inductor is selected to be very small and
inductor ripple current is high, output capacitor could be
overstressed.
Loop Compensation
AOZ1012D employs peak current mode control for easy
use and fast transient response. Peak current mode
control eliminates the double pole effect of the output
L&C filter. It greatly simplifies the compensation loop
design.
With peak current mode control, the buck power stage
can be simplified to be a one-pole and one-zero system
in frequency domain. The pole is dominant pole and can
be calculated by:
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f p1
=
2π
1
× CO
×
RL
The zero is a ESR zero due to output capacitor and its
ESR. It is can be calculated by:
fZ1
=
2π
1
× CO ×
ESRCO
Where
CO is the output filter capacitor;
RL is load resistor value;
ESRCO is the equivalent series
output capacitor;
resistance
of
The compensation design is actually to shape the
converter close loop transfer function to get desired
gain and phase. Several different types of compensation
network can be used for AOZ1012D. For most cases, a
series capacitor and resistor network connected to the
COMP pin sets the pole-zero and is adequate for a
stable high-bandwidth control loop.
In AOZ1012D, FB pin and COMP pin are the inverting
input and the output of internal transconductance error
amplifier. A series R and C compensation network
connected to COMP provides one pole and one zero.
The pole is:
f p2
=
2π
GEA
× CC × GVEA
Where GEA is the error amplifier transconductance,
which is 200·10-6 A/V;
GVEA is the error amplifier voltage gain,
which is 500 V/V;
CC is compensation capacitor;
The zero given by the external compensation network,
capacitor CC and resistor RC, is located at:
fZ2
=
2π
1
× CC
×
RC
To design the compensation circuit, a target crossover
frequency fC for close loop must be selected. The
system crossover frequency is where control loop has
unity gain. The crossover frequency is the also called
the converter bandwidth. Generally a higher bandwidth
means faster response to load transient. However, the
bandwidth should not be too high because of system
stability concern. When designing the compensation
April 2006
www.aosmd.com
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11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet AOZ1012D.PDF ] | |
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