PDF MT16LD3264A Data sheet ( Hoja de datos )

Número de pieza	MT16LD3264A
Descripción	(MT16LDxx64A) DRAM MODULE
Fabricantes	Micron Technology
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No Preview Available ! www.DataSheet4U.com DRAM MODULE 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs MT8LD864A X, MT16LD1664A X, MT32LD3264A X For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/datasheets/datasheet.html FEATURES • Eight-CAS# ECC pinout in a 168-pin, dual in-line memory module (DIMM) • 64MB (8 Meg x 64), 128MB (16 Meg x 64), and 256MB (32 Meg x 64) • Nonbuffered • High-performance CMOS silicon-gate process • Single +3.3V ±0.3V power supply • All inputs, outputs and clocks are LVTTL- compatible • 4,096-cycle CAS#-BEFORE-RAS# (CBR) refresh distributed across 64ms • Extended Data-Out (EDO) PAGE MODE access cycle • Serial presence-detect (SPD) OPTIONS • Package 168-pin DIMM (gold) MARKING G • Timing 50ns access 60ns access -5 -6 • Access Cycle EDO PAGE MODE X KEY TIMING PARAMETERS SPEED -5 -6 tRC 84ns 104ns tRAC 50ns 60ns tPC 20ns 25ns tAA 25ns 30ns tCAC 13ns 15ns tCAS 8ns 10ns PART NUMBERS PART NUMBER MT8LD864AG-5 X MT8LD864AG-6 X MT16LD1664AG-5 X MT16LD1664AG-6 X MT32LD3264AG-5 X* MT32LD3264AG-6 X* CONFIGURATION 8 Meg x 64 8 Meg x 64 16 Meg x 64 16 Meg x 64 32 Meg x 64 32 Meg x 64 SPEED 50ns 60ns 50ns 60ns 50ns 60ns Contact factory for availability NOTE: Pin symbols in parentheses are not used on these modules but may be used for other modules in this product family. They are for reference only. PIN ASSIGNMENT (Front View) 168-Pin DIMM (H-14; 64MB) (H-17; 128MB) (H-30; 256MB) PIN SYMBOL PIN 1 VSS 43 2 DQ0 44 3 DQ1 45 4 DQ2 46 5 DQ3 47 6 VDD 48 7 DQ4 49 8 DQ5 50 9 DQ6 51 10 DQ7 52 11 DQ8 53 12 VSS 54 13 DQ9 55 14 DQ10 56 15 DQ11 57 16 DQ12 58 17 DQ13 59 18 VDD 60 19 DQ14 61 20 DQ15 62 21 NC 63 22 NC 64 23 VSS 65 24 NC 66 25 NC 67 26 VDD 68 27 WE0# 69 28 CAS0# 70 29 CAS1# 71 30 RAS0# 72 31 OE0# 73 32 VSS 74 33 A0 75 34 A2 76 35 A4 77 36 A6 78 37 A8 79 38 A10 80 39 NC (A12) 81 40 VDD 82 41 VDD 83 42 RFU 84 * 256MB version only SYMBOL VSS OE2# RAS2# CAS2# CAS3# WE2# VDD NC NC NC NC VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 NC RFU NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS NC NC NC SDA SCL VDD PIN SYMBOL PIN SYMBOL 85 VSS 127 VSS 86 DQ32 128 RFU 87 DQ33 129 NC/RAS3# 88 DQ34 130 CAS6# 89 DQ35 131 CAS7# 90 VDD 132 RFU 91 DQ36 133 VDD 92 DQ37 134 NC 93 DQ38 135 NC 94 DQ39 136 NC 95 DQ40 137 NC 96 VSS 138 VSS 97 DQ41 139 DQ48 98 DQ42 140 DQ49 99 DQ43 141 DQ50 100 DQ44 142 DQ51 101 DQ45 143 VDD 102 VDD 144 DQ52 103 DQ46 145 NC 104 DQ47 146 RFU 105 NC 147 NC 106 NC 148 VSS 107 VSS 149 DQ53 108 NC 150 DQ54 109 NC 151 DQ55 110 VDD 152 VSS 111 RFU 153 DQ56 112 CAS4# 154 DQ57 113 CAS5# 155 DQ58 114 NC/RAS1# 156 DQ59 115 RFU 157 VDD 116 VSS 158 DQ60 117 A1 159 DQ61 118 A3 160 DQ62 119 A5 161 DQ63 120 A7 162 VSS 121 A9 163 NC 122 A11 164 NC 123 NC (A13) 165 SA0 124 VDD 166 SA1 125 RFU 167 SA2 126 RFU 168 VDD 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. Micron is a registered trademark of Micron Technology, Inc. 1 page www.DataSheet4U.com WE0# OE0# RAS0# CAS0# CAS1# CAS2# CAS3# A0-A11 WE2# OE2# RAS2# CAS4# CAS5# CAS6# CAS7# 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs FUNCTIONAL BLOCK DIAGRAM MT32LD3264A X (256MB) DQ0-DQ3 DQ4-DQ7 DQ8-DQ11 DQ12-DQ15 DQ16-DQ19 DQ20-DQ23 DQ24-DQ27 DQ28-DQ31 DQ0-DQ3 WE# OE# U1 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U2 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U3 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U4 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U5 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U6 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U7 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U8 RAS# CAS# A0ÐA11 12 DQ32-DQ35 DQ36-DQ39 DQ40-DQ43 DQ44-DQ47 DQ48-DQ51 DQ52-DQ55 DQ56-DQ59 DQ60-DQ63 DQ0-DQ3 WE# OE# U9 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U10 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U11 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U12 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U13 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U14 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U15 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U16 RAS# CAS# A0ÐA11 12 RAS1# RAS3# DQ0-DQ3 DQ4-DQ7 DQ8-DQ11 DQ12-DQ15 DQ16-DQ19 DQ20-DQ23 DQ24-DQ27 DQ28-DQ31 DQ0-DQ3 WE# OE# U17 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U18 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U19 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U20 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U21 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U22 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# U23 OE# RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U24 RAS# CAS# A0ÐA11 12 DQ32-DQ35 DQ36-DQ39 DQ40-DQ43 DQ44-DQ47 DQ48-DQ51 DQ52-DQ55 DQ56-DQ59 DQ60-DQ63 DQ0-DQ3 WE# OE# U25 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U26 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U27 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U28 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U29 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U30 RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# U31 OE# RAS# CAS# A0ÐA11 12 DQ0-DQ3 WE# OE# U32 RAS# CAS# A0ÐA11 12 SPD SCL A0 A1 A2 SDA SA0 SA1 SA2 VDD U1-U32 VSS U1-U32 U1-U32 = MT4LC16M4H9 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 5 Page www.DataSheet4U.com 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs EDO PAGE MODE AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 12, 29) (VDD = +3.3V ±0.3V) AC CHARACTERISTICS PARAMETER Access time from column address Column-address setup to CAS# precharge during writes Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Column address to WE# delay time Access time from CAS# Column-address hold time CAS# pulse width CAS# hold time (CBR Refresh) CAS# to output in Low-Z Data output hold after CAS# LOW CAS# precharge time Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) CAS# to WE# delay time WRITE command to CAS# lead time Data-in hold time Data-in setup time Output disable Output enable OE# hold time from WE# during READ-MODIFY-WRITE cycle OE# HIGH hold time from CAS# HIGH OE# HIGH pulse width OE# LOW to CAS# HIGH setup time Output buffer turn-off delay OE# setup prior to RAS# during HIDDEN REFRESH cycle EDO-PAGE-MODE READ or WRITE cycle time EDO-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time Row-address hold time RAS# pulse width RAS# pulse width (EDO PAGE MODE) Random READ or WRITE cycle time RAS# to CAS# delay time READ command hold time (referenced to CAS#) READ command setup time SYMBOL tAA tACH tAR tASC tASR tAWD tCAC tCAH tCAS tCHR tCLZ tCOH tCP tCPA tCRP tCSH tCSR tCWD tCWL tDH tDS tOD tOE tOEH tOEHC tOEP tOES tOFF tORD tPC tPRWC tRAC tRAD tRAH tRAS tRASP tRC tRCD tRCH tRCS -5 MIN MAX 25 12 38 0 0 42 13 8 8 10,000 8 0 3 8 28 5 38 5 30 8 8 0 0 12 12 8 5 5 4 0 12 0 20 47 50 9 9 50 10,000 50 125,000 84 11 0 0 MIN 15 -6 MAX 30 UNITS ns ns 45 ns 0 ns 0 ns 49 ns 15 ns 10 ns 10 10,000 ns 10 ns 0 ns 3 ns 10 ns 35 ns 5 ns 45 ns 5 ns 35 ns 10 ns 10 ns 0 ns 0 15 ns 15 ns 10 ns 10 ns 5 ns 5 ns 0 15 ns 0 ns 25 56 60 12 10 60 10,000 60 125,000 104 14 0 0 ns ns ns ns ns ns ns ns ns ns ns NOTES 23 14 4 15 4 23 22 22 19, 27 19 13 17 16 18 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 11 Page

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