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PDF 74LVC16540A Data sheet ( Hoja de datos )
| Número de pieza | 74LVC16540A | |
| Descripción | CMOS 16-Bit Buffer/Driver | |
| Fabricantes | IDT | |
| Logotipo |  |
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IDT74LVC16540A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
EXTENDEDCOMMERCIALTEMPERATURERANGE
3.3V CMOS 16-BIT
BUFFER/DRIVER
WITH 3-STATE OUTPUTS
AND 5 VOLT TOLERANT I/O
IDT74LVC16540A
FEATURES:
– Typical tSK(0) (Output Skew) < 250ps
– ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
– 0.635mm pitch SSOP, 0.50mm pitch TSSOP
and 0.40mm pitch TVSOP packages
– Extended commercial range of -40°C to +85°C
– VCC = 3.3V ±0.3V, Normal Range
– VCC = 2.7V to 3.6V, Extended Range
– CMOS power levels (0.4µ W typ. static)
– All inputs, outputs and I/O are 5 Volt tolerant
– Supports hot insertion
Drive Features for LVC16540A:
– High Output Drivers: ±24mA
– Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
DESCRIPTION:
This 16-bit buffer driver is built using advanced dual metal CMOS
technology. The 3-state control gate is a 2-input AND gate with active-low
inputs so that if either output-enable (OE1 or OE2) input is high, all
corresponding outputs are in the high-impedance state. To ensure the high-
impedance state during power up or power down, OE should be tied to Vcc
through a pullup resistor; the minimum value of the resistor is determined
by the current-sinking capabiltiy of the driver.
All pins of this 16-bit buffer/line driver can be driven from either 3.3V or
5V devices. This feature allows the use of this device as a translator in a
mixed 3.3V/5V supply system.
The LVC16540A has been designed with a ±24mA output driver. The
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
FUNCTIONAL BLOCK DIAGRAM
1OE1 1
48
1OE2
47
1A1
2OE1 24
25
2OE2
2 1Y1
36
2A1
13 2Y1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
c 1999 Integrated Device Technology, Inc.
1
OCTOBER 1999
DSC-4700/-
1 page  
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IDT74LVC16540A
3.3V CMOS 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
EXTENDEDCOMMERCIALTEMPERATURERANGE
TEST CIRCUITS AND WAVEFORMS:
TEST CONDITIONS
PROPAGATION DELAY
Symbol VCC(1)= 3.3V ±0.3V VCC(1) = 2.7V VCC(2)= 2.5V ±0.2V Unit
VLOAD
VIH
VT
VLZ
VHZ
CL
6
2.7
1.5
300
300
50
6
2 x Vcc
V
2.7 Vcc V
1.5
VCC / 2
V
300 150 mV
300 150 mV
50 30 pF
LVC Link
TEST CIRCUITS FOR ALL OUTPUTS
VCC
VLOAD
Open
Pulse (1, 2)
Generator
VIN
VOUT
D.U.T.
500Ω
GND
RT
500Ω
CL
DEFINITIONS:
LVC Link
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
SAME PHASE
INPUT TRANSITION
OUTPUT
tPLH
OPPOSITE PHASE
INPUT TRANSITION
tPLH
tPHL
tPHL
VIH
VT
0V
VOH
VT
VOL
VIH
VT
0V
LVC Link
ENABLE AND DISABLE TIMES
CONTROL
IN P U T
ENABLE
tPZL
DISABLE
tPLZ
VIH
VT
0V
OUTPUT SWITCH
NORMALLY CLOSED
LOW
tPZH
OUTPUT SWITCH
NORMALLY OPEN
HIGH
V LO AD/2
VT
tPHZ
VT
0V
VLOAD/2
VOL+VLZ
VOL
VOH
VOH-VHZ
0V
NOTE:
LVC Link
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
SWITCH POSITION
SET-UP, HOLD, AND RELEASE TIMES
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
OUTPUT SKEW - tsk (x)
Switch
VLOAD
GND
Open
DATA
IN P U T
TIMING
IN P U T
LVC Link
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
IN P U T
OUTPUT 1
OUTPUT 2
tPLH1
tPHL1
tSK (x)
tSK (x)
VIH
VT
0V
VOH
VT
VOL
VOH
VT
VOL
tPLH2
tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
NOTES:
LVC Link
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
PULSE WIDTH
LO W -H IG H -LO W
PULSE
H IG H -LO W -H IG H
PULSE
5
tSU tH
tREM
tSU tH
tW
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
LVC Link
VT
VT
LVC Link
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet 74LVC16540A.PDF ] | |
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