PDF AT25DF321 Data sheet ( Hoja de datos )

Número de pieza	AT25DF321
Descripción	32M-Bit Serial Firmware Dataflash Memory
Fabricantes	ATMEL Corporation
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No Preview Available ! www.DataSheet4U.com Features • Single 2.7V - 3.6V Supply • Serial Peripheral Interface (SPI) Compatible – Supports SPI Modes 0 and 3 • 70 MHz Maximum Clock Frequency • Flexible, Uniform Erase Architecture – 4-Kbyte Blocks – 32-Kbyte Blocks – 64-Kbyte Blocks – Full Chip Erase • Individual Sector Protection with Global Protect/Unprotect Feature – Sixty-Four 64-Kbyte Physical Sectors • Hardware Controlled Locking of Protected Sectors • Flexible Programming – Byte/Page Program (1 to 256 Bytes) • Automatic Checking and Reporting of Erase/Program Failures • JEDEC Standard Manufacturer and Device ID Read Methodology • Low Power Dissipation – 7 mA Active Read Current (Typical) – 4 µA Deep Power-Down Current (Typical) • Endurance: 100,000 Program/Erase Cycles • Data Retention: 20 Years • Complies with Full Industrial Temperature Range • Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options – 8-lead SOIC (200-mil wide) – 16-lead SOIC (300-mil wide) 32-megabit 2.7-volt Only Serial Firmware DataFlash® Memory AT25DF321 1. Description The AT25DF321 is a serial interface Flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shad- owed from Flash memory into embedded or external RAM for execution. The flexible erase architecture of the AT25DF321, with its erase granularity as small as 4-Kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage EEPROM devices. The physical sectoring and the erase block sizes of the AT25DF321 have been opti- mized to meet the needs of today's code and data storage applications. By optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently. Because certain code modules and data storage segments must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with large sectored and large block erase Flash memory devices can be greatly reduced. This increased memory space efficiency allows addi- tional code routines and data storage segments to be added while still maintaining the same overall device density. 3669A–DFLASH–07/07 1 page www.DataSheet4U.com Figure 4-1. Memory Architecture Diagram Block Erase Detail Internal Sectoring for Sector Protection Function 64KB (Sector 63) 64KB (Sector 62) 64KB 32KB 4KB Block Erase Block Erase Block Erase (D8h Command) (52h Command) (20h Command) Block Address Range 64KB 32KB 32KB 64KB 32KB 32KB 4KB 3FFFFFh – 3FF000h 4KB 3FEFFFh – 3FE000h 4KB 3FDFFFh – 3FD000h 4KB 3FCFFFh – 3FC000h 4KB 3FBFFFh – 3FB000h 4KB 3FAFFFh – 3FA000h 4KB 3F9FFFh – 3F9000h 4KB 3F8FFFh – 3F8000h 4KB 3F7FFFh – 3F7000h 4KB 3F6FFFh – 3F6000h 4KB 3F5FFFh – 3F5000h 4KB 3F4FFFh – 3F4000h 4KB 3F3FFFh – 3F3000h 4KB 3F2FFFh – 3F2000h 4KB 3F1FFFh – 3F1000h 4KB 3F0FFFh – 3F0000h 4KB 3EFFFFh – 3EF000h 4KB 3EEFFFh – 3EE000h 4KB 3EDFFFh – 3ED000h 4KB 3ECFFFh – 3EC000h 4KB 3EBFFFh – 3EB000h 4KB 3EAFFFh – 3EA000h 4KB 3E9FFFh – 3E9000h 4KB 3E8FFFh – 3E8000h 4KB 3E7FFFh – 3E7000h 4KB 3E6FFFh – 3E6000h 4KB 3E5FFFh – 3E5000h 4KB 3E4FFFh – 3E4000h 4KB 3E3FFFh – 3E3000h 4KB 3E2FFFh – 3E2000h 4KB 3E1FFFh – 3E1000h 4KB 3E0FFFh – 3E0000h 64KB (Sector 0) 64KB 32KB 32KB 4KB 00FFFFh – 00F000h 4KB 00EFFFh – 00E000h 4KB 00DFFFh – 00D000h 4KB 00CFFFh – 00C000h 4KB 00BFFFh – 00B000h 4KB 00AFFFh – 00A000h 4KB 009FFFh – 009000h 4KB 008FFFh – 008000h 4KB 007FFFh – 007000h 4KB 006FFFh – 006000h 4KB 005FFFh – 005000h 4KB 004FFFh – 004000h 4KB 003FFFh – 003000h 4KB 002FFFh – 002000h 4KB 001FFFh – 001000h 4KB 000FFFh – 000000h AT25DF321 Page Program Detail 1-256 Byte Page Program (02h Command) Page Address Range 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 3FFFFFh – 3FFF00h 3FFEFFh – 3FFE00h 3FFDFFh – 3FFD00h 3FFCFFh – 3FFC00h 3FFBFFh – 3FFB00h 3FFAFFh – 3FFA00h 3FF9FFh – 3FF900h 3FF8FFh – 3FF800h 3FF7FFh – 3FF700h 3FF6FFh – 3FF600h 3FF5FFh – 3FF500h 3FF4FFh – 3FF400h 3FF3FFh – 3FF300h 3FF2FFh – 3FF200h 3FF1FFh – 3FF100h 3FF0FFh – 3FF000h 3FEFFFh – 3FEF00h 3FEEFFh – 3FEE00h 3FEDFFh – 3FED00h 3FECFFh – 3FEC00h 3FEBFFh – 3FEB00h 3FEAFFh – 3FEA00h 3FE9FFh – 3FE900h 3FE8FFh – 3FE800h 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 256 Bytes 0017FFh – 001700h 0016FFh – 001600h 0015FFh – 001500h 0014FFh – 001400h 0013FFh – 001300h 0012FFh – 001200h 0011FFh – 001100h 0010FFh – 001000h 000FFFh – 000F00h 000EFFh – 000E00h 000DFFh – 000D00h 000CFFh – 000C00h 000BFFh – 000B00h 000AFFh – 000A00h 0009FFh – 000900h 0008FFh – 000800h 0007FFh – 000700h 0006FFh – 000600h 0005FFh – 000500h 0004FFh – 000400h 0003FFh – 000300h 0002FFh – 000200h 0001FFh – 000100h 0000FFh – 000000h 3669A–DFLASH–07/07 5 5 Page www.DataSheet4U.com AT25DF321 If the address specified by A23-A0 points to a memory location within a sector that is in the pro- tected state, then the Block Erase command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle aborts due to an incomplete address being sent or because a memory location within the region to be erased is protected. While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Regis- ter be polled rather than waiting the tBLKE time to determine if the device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status Register will be reset back to the logical “0” state. The device also incorporates an intelligent erasing algorithm that can detect when a byte loca- tion fails to erase properly. If an erase error arises, it will be indicated by the EPE bit in the Status Register. Figure 8-3. Block Erase CS SCK SI SO 0 1 2 3 4 5 6 7 8 9 10 11 12 26 27 28 29 30 31 OPCODE ADDRESS BITS A23-A0 CCCCCCCCAAAAAA MSB MSB AAAAAA HIGH-IMPEDANCE 8.3 Chip Erase The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip Erase command can be started, the Write Enable command must have been pre- viously issued to the device to set the WEL bit of the Status Register to a logical “1” state. Two opcodes, 60h and C7h, can be used for the Chip Erase command. There is no difference in device functionality when utilizing the two opcodes, so they can be used interchangeably. To perform a Chip Erase, one of the two opcodes (60h or C7h) must be clocked into the device. Since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the device will erase the entire memory array. The erasing of the device is internally self-timed and should take place in a time of tCHPE. The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an even byte boundary (multiples of eight bits); otherwise, no erase will be performed. In addition, if any sector of the memory array is in the protected state, then the Chip Erase command will not be executed, and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical “0” state if a sector is in the protected state. While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device is busy. For faster throughput, it is recommended that the Status Regis- 3669A–DFLASH–07/07 11 11 Page

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