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부품번호 | Z9960 기능 |
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기능 | 200 MHz Multi-Output Zero Delay Buffer | ||
제조업체 | Cypress Semiconductor | ||
로고 | |||
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Z9960
2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buffer
Features
• 2.5V or 3.3V operation
• Output frequency up to 200 MHz
• Supports PowerPC, and Pentium® processors
• 21 clock outputs: drive up to 42 clock lines
• LVPECL or LVCMOS/LVTTL clock input
• Output-to-output skew < 150 ps
• Split 2.5V/3.3V outputs
• Spread spectrum compatible
• Glitch-free output clocks transitioning
• Output disable control
• Pin-compatible with MPC9600
• Industrial temperature range: –40°C to +85°C
• 48-pin LQFP package
Block Diagram
Table 1. Frequency Table[1]
SS
EE
LL
A QA B
0 VCO/2 0
1 VCO/4 1
QB
VCO/2
VCO/4
S
E
L
C
0
1
QC
VCO/2
VCO/4
F
B
_
S
E
L
0
1
FB_OUT
VCO/8
VCO/12
Pin Configuration
REF_SEL
TCLK
PECL_CLK
PECL_CLK#
FB_IN
SELA
SELB
AVDD
PLL
0
1
REF
FB
0
1
/2
/4
/8
/12
A
0
1
DQ
B
0
1
DQ
SELC
C
0
1
DQ
OE#
FB
0
1
DQ
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
FB_OUT
VSS
TCLK
PECL_CLK
PECL_CLK#
VDD
REF_SEL
FB_SEL
AVDD
SELA
SELB
SELC
VSSC
48 47 46 45 44 43 42 41 40 39 38 37
1 36
2 35
3 34
4 33
5
6
Z9960
32
31
7 30
8 29
9 28
10 27
11 26
12 25
13 14 15 16 17 18 19 20 21 22 23 24
VSSA
FB_OUT
QB0
QB1
VDDB
QB2
QB3
VSSB
QB4
QB5
QB6
VDDB
FB_SEL
Note:
1. Input frequency range: 16 MHz to 33 MHz (FB_SEL = 1), or 25 MHz to 50 MHz (FB_SEL = 0).
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07087 Rev. *C
Revised May 03, 2004
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Z9960
Absolute Maximum Ratings[2]
Input Voltage Relative to VSS:...............................VSS – 0.3V
Input Voltage Relative to VDD: ............................. VDD + 0.3V
Storage Temperature: .................................-65°C to + 150°C
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, VIN and VOUT should be constrained to
the range
Operating Temperature: ................................-40°C to + 85°C
Maximum ESD Protection................................................ 2kV
Maximum Power Supply: ................................................5.5V
VSS < (VIN or VOUT) < VDD.
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
Maximum Input Current:..................................................± 20mA
Note:
2. The voltage on any input or I/O or pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Characteristics VDD = 2.5V ±5%, TA = –40°C to +85°C
Parameter
VIL[3]
VIH[3]
VPP
VCMR[4]
IIL[5]
IIH[5]
VOL[6]
VOH[6]
IDD
CIN
Description
Input Low Voltage
Input High Voltage
Peak-to-Peak Input Voltage
PECL_CLK
Common Mode Range
PECL_CLK
Input Low Current (@ VIL = VSS)
Input High Current (@ VIH =
VDD)
Output Low Voltage
Output High Voltage
Quiescent Supply Current
Input Pin Capacitance
Test Condition
IOL = 15 mA
IOH = –15 mA
VDD and AVDD
Min.
VSS
1.7
500
VDD –1.4
–
–
–
1.8
–
–
Typ.
–
–
–
–
–
–
–
–
10
4
Max.
0.7
VDD
1000
Unit
V
V
mV
VDD –0.6
–120
120
V
µA
µA
0.6 V
V
13 mA
– pF
DC Electrical Characteristics VDD = 3.3V +5%, TA = –40°C to +85°C
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
VIL[3]
VIH[3]
Input Low Voltage
Input High Voltage
VSS –
0.8 V
2.0
–
VDD
V
VPP Peak-to-Peak Input Voltage
PECL_CLK
500
–
1000
mV
VCMR[4]
IIL[5]
IIH[5]
VOL[6]
VOH[6]
Common Mode Range PECL_CLK
Input Low Current (@ VIL = VSS)
Input High Current (@ VIH = VDD)
Output Low Voltage
Output High Voltage
IOL = 24 mA
IOH = –24 mA
VDD –1.4
–
VDD –0.6
V
–
–
–120
µA
– – 120 µA
– – 0.55 V
2.4 –
–V
IDD Quiescent Supply Current
VDD and AVDD
– 15 20 mA
CIN Input Pin Capacitance
– 4 – pF
Notes:
3. The LVCMOS inputs threshold is at 30% of VDD.
4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when HIGH input is within the VCMR range
and the input lies within the VPP specification.
5. Inputs have pull-up/pull-down resistors that affect input current.
6. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines.
Document #: 38-07087 Rev. *C
Page 4 of 7
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Z9960
Document History
Document Title: Z9960 2.5V/3.3V, 200 MHz Multi-Output Zero Delay Buffer
Document #: 38-07087 Rev. *C
Rev. ECN No.
Issue
Date
Orig. of
Change
Description of Change
** 107123 06/06/01
IKA Convert from IMI to Cypress
*A
108715
11/07/01
NDP
Updated AVDD Pin Functionality.
*B 122772 12/21/02
RBI Add power up requirements to maximum ratings information
*C 223804 See ECN
RGL
Corrected the Ordering information entry
Document #: 38-07087 Rev. *C
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부품번호 | 상세설명 및 기능 | 제조사 |
Z9960 | 200 MHz Multi-Output Zero Delay Buffer | Cypress Semiconductor |
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