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MK2304-2 데이터시트 PDF




ICS에서 제조한 전자 부품 MK2304-2은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 MK2304-2 기능
기능 LOW SKEW BUFFER
제조업체 ICS
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MK2304-2 데이터시트, 핀배열, 회로
www.DataSheet4U.com
MK2304-2
ZERO DELAY, LOW SKEW BUFFER
Description
The MK2304-2 is a low jitter, low skew, high
performance Phase Lock Loop (PLL) based zero delay
buffer for high speed applications. Based on ICS’
proprietary low jitter PLL techniques, the device
provides four low skew outputs at speeds up to 133
MHz at 3.3 V. The MK2304-2 includes a bank of two
outputs running at 1/2X. In the zero delay mode, the
rising edge of the input clock is aligned with the rising
edges of all 4 outputs. Compared to competitive CMOS
devices, the MK2304-2 has the lowest jitter.
The MK2304-2 PLL enters a power-down state when
there are no rising edges on the REF input. In this
mode, all outputs are tri-stated and the PLL is turned
off, resulting in leass than 25 µA of current draw.
ICS manufactures the largest variety of clock
generators and buffers and is the largest clock supplier
in the world.
Features
Packaged in 8 pin SOIC
Zero input-output delay
Two 1X outputs plus two 1/2X outputs
Output to output skew is less than 200 ps
Output clocks up from 10 MHz to 133 MHz at 3.3 V
Ability to generate 2X the input
Full CMOS outputs with 18 mA output drive
capability at TTL levels at 3.3 V
Spread SmartTM technology works with spread
spectrum clock generators
Advanced, low power, sub micron CMOS process
Operating voltage of 3.3 V
Available in industial temperature operation
Available in Pb (lead) free package
Low Standby Current
Block Diagram
VDD
1
FBIN
CLKIN
PLL
CLKA1
CLKA2
BANK
A
CLKB1
BANK
/2 B
CLKB2
1
GND
MDS 2304-2 C
1
Revision 050306
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com




MK2304-2 pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
MK2304-2
ZERO DELAY, LOW SKEW BUFFER
AC Electrical Characteristics
VDD = 3.3V ±10%, Ambient Temperature -40° C to 85° C
Parameter
Symbol
Conditions
Output Frequency
FBIN to CLKA1,
30 pF Load
Output Frequency
FBIN to CLKA1,
15 pf Load
Output Rise Time
Output Rise Time
Output Fall Time
Output Fall Time
Output Clock Duty Cycle
Output Clock Duty Cycle
Device-to-Device skew, equally
loaded
tOR 0.8 to 2.0 V, CL=30 pF
tOR 0.8 to 2.0 V, CL=15 pF
tOF 0.8 to 2.0 V, CL=30 pF
tOF 0.8 to 2.0 V, CL=15 pF
At 1.4 V, CL=30 pf
At 1.4 V, CL=15 pf
Rising edges at VDD/2
Output-to-Output skew, equally
loaded, On same bank
Rising edges at VDD/2
Skew from Output Bank A to
Output Bank B
All outputs equally
loaded
Delay CLKIN Rising Edge to
FBIN Rising Edge
Measured at VDD/2
Cycle-to-Cycle Jitter
30 pF loads
66.67 MHz outputs
15 pF loads
66.67 MHz outputs
PLL Lock Time
tLOCK
Stable power supply,
valid clocks on CLKIN,
FBIN
Min.
10
10
40
45
Typ. Max. Units
100 MHz
133 MHz
2.2
1.5
2.2
1.5
50 60
50 65
500
ns
ns
ns
ns
%
%
ps
200 ps
400 ps
±250 ps
400 ps
375 ps
1 ms
Thermal Characteristics
Parameter
Symbol Conditions
Thermal Resistance Junction to
Ambient
θJA Still air
θJA 1 m/s air flow
θJA 3 m/s air flow
Thermal Resistance Junction to Case θJC
Min.
Typ.
120
115
105
58
Max.
Units
°C/W
°C/W
°C/W
°C/W
MDS 2304-2 C
4
Revision 050306
Integrated Circuit Systems 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com

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MK2304-2

LOW SKEW BUFFER

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