PDF ICS951416 Data sheet ( Hoja de datos )

Número de pieza	ICS951416
Descripción	System Clock Chip
Fabricantes	ICS
Logotipo
Hay una vista previa y un enlace de descarga de ICS951416 (archivo pdf) en la parte inferior de esta página. Total 25 Páginas
No Preview Available ! www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS951416 System Clock Chip for ATI RS480 Recommended Application: ATI RS480 systems using AMD K8 processors Output Features: • 3 - 14.318 MHz REF clocks • 1 - USB_48MHz USB clock • 1 - HyperTransport 66 MHz clock seed • 1 - PCI 33 MHz clock seed • 2 - Pairs of AMD K8 clocks • 6 - Pairs of SRC/PCI Express* clocks • 2 - Pairs of ATIG (SRC/PCI Express) clocks Features: • 2 - Programmable Clock Request pins for SRC clocks • ATIGCLKS are programmable for frequency • Spread Spectrum for EMI reduction • Outputs may be disabled via SMBus • External crystal lead capacitors for maximum frequency accuracy Pin Configuration X1 1 X2 2 VDD48 3 USB_48MHz 4 GND 5 NC 6 SCLK 7 SDATA 8 FS2 9 CLKREQA# 10 CLKREQB# 11 SRCCLKT7 12 SRCCLKC7 13 VDDSRC 14 GNDSRC 15 SRCCLKT6 16 SRCCLKC6 17 SRCCLKT5 18 SRCCLKC5 19 GNDSRC 20 VDDSRC 21 SRCCLKT4 22 SRCCLKC4 23 SRCCLKT3 24 SRCCLKC3 25 GNDSRC 26 ATIGCLKT1 27 ATIGCLKC1 28 56 VDDREF 55 GND 54 FS0/REF0 53 FS1/REF1 52 REF2 51 VDDPCI 50 PCICLK0 49 GNDPCI 48 VDDHTT 47 HTTCLK0 46 GNDHTT 45 CPUCLK8T0 44 CPUCLK8C0 43 VDDCPU 42 GNDCPU 41 CPUCLK8T1 40 CPUCLK8C1 39 VDDA 38 GNDA 37 IREF 36 GNDSRC 35 VDDSRC 34 SRCCLKT0 33 SRCCLKC0 32 VDDATI 31 GNDATI 30 ATIGCLKT0 29 ATIGCLKC0 Note: Pins preceeded by '' have a 120 Kohm Internal Pull Down resistor 56 Pin SSOP/TSSOP Power Groups Pin Number VDD GND 56 55 51 49 48 46 43 14, 21, 32,35 39 42 15, 20, 26,31,36 38 35 0937G—04/29/05 Description Xtal, REF PCICLK output HTTCLK output CPU Outputs SRC outputs Analog, CPU PLL USB_48MHz output Functionality FS2 FS1 00 00 01 01 10 10 11 FS0 0 1 0 1 0 1 1 CPU MHz Hi-Z X 180.00 220.00 100.00 133.33 200.00 HTT MHz Hi-Z X/3 60.00 73.12 66.66 66.66 66.66 PCI MHz Hi-Z X/6 30.00 36.56 33.33 33.33 33.33 Other names and brands may be claimed as the property of others. 1 page www.DataSheet4U.com ICS951416 General SMBus serial interface information How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D2 (H) • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS clock will acknowledge • Controller (host) sends the data byte count = X • ICS clock will acknowledge • Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) • ICS clock will acknowledge each byte one at a time • Controller (host) sends a Stop bit How to Read: • Controller (host) will send start bit. • Controller (host) sends the write address D2 (H) • ICS clock will acknowledge • Controller (host) sends the begining byte location = N • ICS clock will acknowledge • Controller (host) will send a separate start bit. • Controller (host) sends the read address D3 (H) • ICS clock will acknowledge • ICS clock will send the data byte count = X • ICS clock sends Byte N + X -1 • ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). • Controller (host) will need to acknowledge each byte • Controllor (host) will send a not acknowledge bit • Controller (host) will send a stop bit Index Block Write Operation Controller (Host) ICS (Slave/Receiver) T starT bit Slave Address D2(H) WR WRite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK Byte N + X - 1 P stoP bit ACK 0937G—04/29/05 5 Index Block Read Operation Controller (Host) ICS (Slave/Receiver) T starT bit Slave Address D2(H) WR WRite ACK Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK ACK ACK Data Byte Count = X Beginning Byte N N Not acknowledge P stoP bit Byte N + X - 1 5 Page www.DataSheet4U.com ICS951416 SMBus Table: Device ID Register Byte 6 Pin # Name Bit 7 - DevID 7 Bit 6 - DevID 6 Bit 5 - DevID 5 Bit 4 - DevID 4 Bit 3 - DevID 3 Bit 2 - DevID 2 Bit 1 Bit 0 - - DevID 1 DevID 0 Control Function Device ID MSB Device ID 6 Device ID 5 Device ID4 Device ID3 Device ID2 Device ID1 Device ID LSB Type R R R R R R R R 0 - - - - - - - - 1 PWD -0 -0 -0 -1 -0 -1 -1 -0 SMBus Table: Vendor ID Register Byte 7 Pin # Name Bit 7 - RID3 Bit 6 - RID2 Bit 5 - RID1 Bit 4 - RID0 Bit 3 - VID3 Bit 2 - VID2 Bit 1 - VID1 Bit 0 - VID0 Control Function Revision ID VENDOR ID (0001 = ICS) Type R R R R R R R R 0 - - - - - - - - 1 PWD -X -X -X -X -0 -0 -0 -1 SMBus Table: Byte Count Register Byte 8 Pin # Name Bit 7 - BC7 Bit 6 - BC6 Bit 5 - BC5 Bit 4 - BC4 Bit 3 - BC3 Bit 2 - BC2 Bit 1 - BC1 Bit 0 - BC0 Control Function Byte Count Programming b(7:0) Type 0 1 RW RW RW Writing to this register RW will configure how many RW bytes will be read back, RW default is 9 bytes. RW RW PWD 0 0 0 0 1 0 0 1 SMBus Table: WD TimeR Control Register Byte 9 Pin # Name Control Function Bit 7 - WDH_EN Watchdog Hard Alarm Enable Bit 6 - WDS_EN Watchdog Soft Alarm Enable Bit 5 - WD Hard Status WD Hard Alarm Status Bit 4 - WD Soft Status WD Soft Alarm Status Bit 3 - WDTCtrl Watch Dog Time base Control Bit 2 - WD2 WD Timer Bit 2 Bit 1 - WD1 WD Timer Bit 1 Bit 0 - WD0 WD Timer Bit 0 Type 0 RW Disable 1 Enable RW Disable Enable R Normal Alarm R Normal Alarm RW 290ms Base 1160ms Base RW These bits represent RW X290ms (or 1.16S) the RW watchdog timer waits 0937G—04/29/05 PWD 0 0 X X 0 1 1 1 11 11 Page

Páginas	Total 25 Páginas
PDF Descargar	[ Datasheet ICS951416.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
ICS951411	System Clock Chip	ICS
ICS951412	System Clock Chip	ICS
ICS951413	Programmable System Clock Chip	ICS
ICS951416	System Clock Chip	ICS

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar