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PDF K6R4016V1C Data sheet ( Hoja de datos )
| Número de pieza | K6R4016V1C | |
| Descripción | 256Kx16 Bit High Speed Static RAM | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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PRELIMPreliminaryPPPPPPPPPINARY
K6R4016V1C-C/C-L, K6R4016V1C-I/C-P
CMOS SRAM
Document Title
256Kx16 Bit High Speed Static RAM(3.3V Operating).
Operated at Commercial and Industrial Temperature Ranges.
Revision History
RevNo. History
Rev. 0.0 Initial release with Preliminary.
Rev. 1.0
1.1 Removed Low power Version.
1.2 Removed Data Retention Characteristics.
1.3 Changed ISB1 to 20mA
Rev. 2.0
Relax D.C parameters.
Item
12ns
ICC 15ns
20ns
Previous
180mA
175mA
170mA
Current
200mA
195mA
190mA
Draft Data
Remark
Feb. 12. 1999 Preliminary
Mar. 29. 1999 Preliminary
Aug. 19. 1999 Preliminary
Rev. 3.0
3.1 Delete Preliminary
3.2 Update D.C parameters and 10ns part.
Previous
ICC Isb Isb1 ICC
10ns
-
160mA
12ns
15ns
200mA
195mA
70mA
20mA
150mA
140mA
20ns 190mA
130mA
Current
Isb
60mA
Isb1
10mA
Mar. 27. 2000 Final
Rev. 4.0
Rev. 5.0
Add Low Power-Ver.
Delete 20ns speed bin
Apr. 24. 2000 Final
Sep. 24. 2001 Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 5.0
September 2001
1 page  
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PRELIMPreliminaryPPPPPPPPPINARY
K6R4016V1C-C/C-L, K6R4016V1C-I/C-P
CMOS SRAM
AC CHARACTERISTICS(TA=0 to 70°C, VCC=3.3±0.3V, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
* The above test conditions are also applied at industrial temperature range.
Value
0V to 3V
3ns
1.5V
See below
Output Loads(A)
DOUT
ZO = 50Ω
Output Loads(B)
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
RL = 50Ω
VL = 1.5V
30pF*
DOUT
353Ω
+3.3V
319Ω
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
READ CYCLE*
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
UB, LB Access Time
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
UB, LB Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
UB, LB Disable to High-Z Output
Output Hold from Address Change
Symbol
tRC
tAA
tCO
tOE
tBA
tLZ
tOLZ
tBLZ
tHZ
tOHZ
tBHZ
tOH
K6R4016V1C-10
Min Max
10 -
- 10
- 10
-5
-5
3-
0-
0-
05
05
05
3-
* The above parameters are also guaranteed at industrial temperature range.
K6R4016V1C-12
Min Max
12 -
- 12
- 12
-6
-6
3-
0-
0-
06
06
06
3-
K6R4016V1C-15
Min Max
15 -
- 15
- 15
-7
-7
3-
0-
0-
07
07
07
3-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-5-
Rev 5.0
September 2001
5 Page 
www.DataSheet4U.com
PRELIMPreliminaryPPPPPPPPPINARY
K6R4016V1C-C/C-L, K6R4016V1C-I/C-P
CMOS SRAM
PACKAGE DIMENSIONS
Top View
Bottom View
Units : millimeter.
B
#A1
6
A
B
C
D
E
F
G
H
B
B1
5 4 3 21
A1 INDEX MARK
0.50
0.50
B/2
Side View
D
C
Min Typ Max
A - 0.75 -
B 8.90 9.00 9.10
B1 - 3.75 -
C 8.90 9.00 9.10
C1 - 5.25 -
D 0.30 0.35 0.40
E - 1.05 1.20
E1 - 0.80 -
E2 0.20 0.25 0.30
Y-
- 0.08
Detail A
A
Y
Notes.
1. Bump counts: 48(8row x 6column)
2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)
3. All tolerence are +/-0.050 unless
otherwise specified.
4. Typ : Typical
5. Y is coplanarity: 0.08(Max)
- 11
Rev 5.0
September 2001
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet K6R4016V1C.PDF ] | |
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