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PDF E8870 Data sheet ( Hoja de datos )
| Número de pieza | E8870 | |
| Descripción | Intel E8870 Scalable Node Controller | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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Intel® E8870 Scalable Node Controller
(SNC) Datasheet
Product Features
s Intel® Itanium® 2 Processor System Bus
— Itanium 2 processor system bus
interface (44-bit address, 128-bit data)
at 400 MHz data bus frequency
— Full multiprocessor support for up to
four Itanium 2 processors on the system
bus
— Parity protection on address and control
signals
— ECC protection on each 64-bit chunk of
the 128-bit data signals on the
Itanium 2 processor system bus
— Eight-deep in-order queue
— Non-blocking transaction handling::
Transactions receive Normal
Completion, Retry, or Defer;
All transactions normally deferred;
No chipset snoop stalls
— GTL+ bus driver technology
— Chipset adds only one load to the
system bus
s PC1600 DDR SDRAM Memory via DDR
Memory Hub (DMH)
— Supports up to four DMHs
— 1, 2, 3, or 4 different types of DIMMs
per branch channel
— Supports 128-, 256-, 512-, 1024-Mb
devices in X4 and X8 configurations
— Supports from 512 MB (128 Mb
devices) to 128 GB (1 Gb devices) of
memory in 128 MB increments
— 6.4 GB/s peak bandwidth
— Server Error Correction Code corrects
for any single failed X4 memory
device, and limited correction on data
errors from X8 memory devices
— ECC with error correction and periodic
scrubbing of the memory
s Scalability Port (SP)
— Two SPs with 3.2 GB/s peak bandwidth
per direction per SP
— Bidirectional SPs for a total bandwidth
of 12.8 GB/s
s Firmware
— Firmware hub interface for processor-
specific firmware
s Reliability, Availability, and Serviceability
(RAS)
— Sideband access to configuration
registers via SMBus or JTAG.
— End-to-end ECC for all interfaces
— Fault detection and logging
— Signal connectivity testing via
boundary scan
s Packaging
— 49.5mm x 49.5mm
— 1357-pin organic LAN grid array
(OLGA) package-2B
Document Number: 251112-001
August 2002
1 page  
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3.10.11 FSBPMEU[1:0]: Processor Bus Perform Monitor
Utilization Events.................................................................................3-55
3.10.12 SPPMD[1:0]: SP Performance Monitor Data.......................................3-57
3.10.13 SPPMC[1:0]: SP Performance Compare ............................................3-57
3.10.14 SPPMR[1:0]: SP Performance Monitor Response ..............................3-58
3.10.15 SPPME[1:0]: SP Performance Monitor Events ...................................3-60
3.10.16 HPPMR: Hot Page Control and Response..........................................3-61
3.10.17 HPADDR: Hot Page Index ..................................................................3-63
3.10.18 HPDATA: Hot Page Data ....................................................................3-63
3.10.19 HPCMP: Hot Page Count Compare ....................................................3-63
3.10.20 HPBASE: Hot Page Range Base ........................................................3-64
3.10.21 HPMAX: Hot Page Max Range Address .............................................3-64
3.10.22 HPRCTR: Hot Page Range Counter ...................................................3-65
4 System Address Map ......................................................................................................4-1
4.1 Memory Map ......................................................................................................4-1
4.1.1 Compatibility Region .............................................................................4-2
4.1.2 System Region ......................................................................................4-3
4.1.3 High and Low Memory Mapped I/O (MMIO) .........................................4-7
4.1.4 Memory Mapped Configuration Space..................................................4-8
4.1.5 Main Memory Region ............................................................................4-8
4.2 Memory Address Disposition............................................................................4-12
4.2.1 Registers Used for Address Routing ...................................................4-12
4.2.2 Inbound Transactions to SIOH ............................................................4-16
4.2.3 Local/Remote Decoding for Requests to Main Memory......................4-18
4.2.4 Default SP Requirement in Single Node .............................................4-18
4.3 I/O Address Map ..............................................................................................4-18
4.3.1 Special I/O addresses .........................................................................4-18
4.3.2 Outbound I/O Access ..........................................................................4-19
4.3.3 Inbound I/Os........................................................................................4-20
4.4 Configuration Space.........................................................................................4-20
4.5 Illegal Addresses ..............................................................................................4-21
4.5.1 Master Abort........................................................................................4-21
4.5.2 Processor Requests ............................................................................4-21
4.5.3 Scalability Port Requests ....................................................................4-21
5 Memory Subsystem.........................................................................................................5-1
5.1 Memory Controller Operation .............................................................................5-1
5.1.1 Memory Arbitration ................................................................................5-1
5.1.2 Reads ....................................................................................................5-2
5.1.3 Writes ....................................................................................................5-3
5.2 Error Correction..................................................................................................5-4
5.2.1 Scrub Address Generation ....................................................................5-4
5.2.2 Correction for System Accesses ...........................................................5-5
5.2.3 Software Scrubs ....................................................................................5-5
5.2.4 Memory Error Correction Code .............................................................5-5
5.2.5 Memory Device Failure Correction and Failure Isolation ......................5-8
5.2.6 Memory Test .........................................................................................5-8
5.3 DDR Organization ..............................................................................................5-9
5.3.1 DDR Configuration Rules ......................................................................5-9
5.3.2 DDR Features Supported....................................................................5-10
5.3.3 Power Management ............................................................................5-14
5.3.4 DDR Maintenance Operations ............................................................5-15
Intel® E8870 Scalable Node Controller (SNC) Datasheet v
5 Page 
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Introduction
1
1.1 Overview
The Intel® E8870 chipset delivers new levels of availability, features and performance for servers.
It provides flexible common modular architecture support for the Intel® Itanium® 2 processors.
The Intel E8870 chipset supports up to four processors, and up to eight processors with the
Scalability Port Switch (SPS) component, delivering stability to the platforms through reuse and
common architecture support.
The component names used throughout this document refer to the component markings listed in
Table 1-1.
Table 1-1. Chipset Component Markings
Component Name
SNC
SIOH
SPS
DMH
P64H2
ICH4
FWH
Product Marking
E8870
E8870IO
E8870SP
E8870DH
82870P2
82801DB
82802AC
1.2
Scalable Node Controller (SNC) Overview
The SNC is the processor system bus interface and memory controller for the E8870 chipset. It
supports the Itanium 2 processors, DDR SDRAM main memory, a firmware hub interface to
support multiple firmware hubs, two scalability ports (SPs) for access to I/O and coherent memory
on other nodes.
The SNC may be connected to a SPS for scaling to large systems as shown in Figure 1-1. The SNC
is connected directly to an SIOH for single-node system implementations.
Intel® E8870 Scalable Node Controller (SNC) Datasheet
1-1
11 Page | ||
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| PDF Descargar | [ Datasheet E8870.PDF ] | |
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