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기능 256Mb M-die MLC NOR Specification
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K8F5715EBM 데이터시트, 핀배열, 회로
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K8F56(57)15ET(B)M
NOR FLASH MEMORY
256Mb M-die MLC NOR Specification
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
1 Revision 1.2
September, 2006




K8F5715EBM pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
K8F56(57)15ET(B)M
NOR FLASH MEMORY
256M Bit (16M x16) Muxed Burst , Multi Bank MLC NOR Flash Memory
FEATURES
GENERAL DESCRIPTION
Single Voltage, 1.7V to 1.95V for Read and Write operations
The K8F56(57)15E featuring single 1.8V power supply is a
Organization
256Mbit Muxed Burst Multi Bank Flash Memory organized as
- 16,777,216 x 16 bit (Word Mode Only)
Multiplexed Data and Address for reduction of interconnections
- A/DQ0 ~ A/DQ15
Read While Program/Erase Operation
Multiple Bank Architecture
- 16 Banks (16Mb Partition)
OTP Block : Extra 512-Word block
Read Access Time (@ CL=30pF)
16Mx16. The memory architecture of the device is designed to
divide its memory arrays into 259 blocks with independent hard-
ware protection. This block architecture provides highly flexible
erase and program capability. The K8F56(57)15E NOR Flash
consists of sixteen banks. This device is capable of reading
data from one bank while programming or erasing in the other
bank.
- Asynchronous Random Access Time : 100ns
Regarding read access time, the K8F5615E provides an 11ns
- Synchronous Random Access Time : 100ns
burst access time and an 100ns initial access time at 66MHz. At
- Burst Access Time :
83MHz, the K8F5615E provides an 9ns burst access time and
11ns (66MHz), 9ns(83MHz), 7ns (108MHz), 6ns(133MHz)
an 100ns initial access time. At 108MHz, the K8F5715E pro-
Burst Length :
vides an 7ns burst access time and an 100ns initial access
- Continuous Linear Burst
- Linear Burst : 8-word & 16-word with No-wrap & Wrap
Block Architecture
- Four 16Kword blocks and two hundreds fifty-five 64Kword blocks
time. At 133MHz, the K8F5715E provides an 6ns burst access
time and an 100ns initial access time.The device performs a
program operation in units of 16 bits (Word) and erases in units
- Bank 0 contains four 16 Kword blocks and fifteen 64Kword blocks
- Bank 1 ~ Bank 15 contain two hundred forty 64Kword blocks
Reduce program time using the VPP
of a block. Single
erase operation is
requires 25mA as
perature ranges.
or multiple blocks can be
completed within typically
program/erase current in
erased. The block
0.6sec. The device
the extended tem-
Support 32 words Buffer Program
The K8F56(57)15E NOR Flash Memory is created by using
Power Consumption (Typical value, CL=30pF)
- Synchronous Read Current : 35mA at 133MHz
- Program/Erase Current : 25mA
Samsung's advanced CMOS process technology. This device is
available in 44ball / 88 ball FBGA package.
- Read While Program/Erase Current : 45mA
PIN DESCRIPTION
- Standby Mode/Auto Sleep Mode : 30uA
Block Protection/Unprotection
Pin Name
Pin Function
- Using the software command sequence
- Last two boot blocks are protected by WP=VIL
A16 - A23 Address Inputs
- All blocks are protected by VPP=VIL
Handshaking Feature
A/DQ0 - A/DQ15 Multiplexed Address/Data input/output
- Provides host system with minimum latency by monitoring RDY
CE Chip Enable
Erase Suspend/Resume
Program Suspend/Resume
OE Output Enable
Unlock Bypass Program/Erase
Hardware Reset (RESET)
RESET
Hardware Reset
Data Polling and Toggle Bits
VPP Accelerates Programming
- Provides a software method of detecting the status of program
or erase completion
WE Write Enable
Endurance
100K Program/Erase Cycles Minimum
WP Hardware Write Protection Input
Data Retention : 10 years
Extended Temperature : -25°C ~ 85°C
CLK Clock
Support Common Flash Memory Interface
RDY
Ready Output
Low Vcc Write Inhibit
Package : 88 - ball FBGA Type (8mm x 11mm),
AVD
Address Valid Input
0.8 mm ball pitch,
1.2mm (Max.) Thickness
DPD
Deep Power Down
44 - ball FBGA Type (8mm x 9mm),
0.5 mm ball pitch,
1.0mm (Max.) Thickness
Vcc Power Supply
VSS Ground
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
4 Revision 1.2
September, 2006

4페이지










K8F5715EBM 전자부품, 판매, 대치품
www.DataSheet4U.com
K8F56(57)15ET(B)M
NOR FLASH MEMORY
ORDERING INFORMATION
K 8 F 56 1 5 E T M - F E 1F
Samsung
NOR Flash Memory
Device Type
MLC Multiplexed Burst
Density
56 = 256Mbits for 66/83MHz
57 = 256Mbits for 108/133MHz
Organization
x16 Organization
Operating Voltage Range
1.7 V to 1.95V
Access Time
Refer to Table 1
Operating Temperature Range
C = Commercial Temp. (0 °C to 70 °C)
E = Extended Temp. (-25 °C to 85 °C)
Package
S : FBGA(Lead Free,OSP)
F : FBGA D : FBGA(Lead Free)
Version
1st Generation
Block Architecture
T = Top Boot Block
B = Bottom Boot Block
Table 1. PRODUCT LINE-UP
Mode
K8F56(57)15ET
Speed Option
1C
(66MHz)
Synchronous/Burst Max. Initial Access Time (tIAA, ns)
Max. Burst Access Time (tBA, ns)
VCC=1.7V
-1.95V
Asynchronous
Max. Access Time (tAA, ns)
Max. CE Access Time (tCE, ns)
Max. OE Access Time (tOE, ns)
100
11
100
100
15
1D
(83MHz)
100
9
100
100
15
1E
(108MHz)
100
7
100
100
15
1F
(133MHz)
100
6
100
100
15
Table 1-1. PRODUCT Classification
Speed/Boot Option
256Mb for 66/83MHz
256Mb for 108/133MHz
Top
K8F5615ETM
K8F5715ETM
Bottom
K8F5615EBM
K8F5715EBM
Table 2. K8F56(57)15E DEVICE BANK DIVISIONS
Bank 0
Mbit
Block Sizes
16 Mbit
Four 16Kwords,
fifteen 64Kwords
Mbit
240 Mbit
Bank 1 ~ Bank 15
Block Sizes
Two hundred
forty 64Kwords
7 Revision 1.2
September, 2006

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256Mb M-die MLC NOR Specification

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