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UXC20P 데이터시트 PDF




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부품번호 UXC20P 기능
기능 DC-20GHz Programmable Binary Prescaler
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UXC20P 데이터시트, 핀배열, 회로
www.DataSheet4U.com
UXC20P - Datasheet
CENTELLAX
DC - 20 GHz Programmable Binary Prescaler
Features
Wide Operating Range: DC - 20GHz
Low SSB Phase Noise: -153 dBc @ 10kHz
Large Output Swings: >1 Vppk/side
Single-Ended and/or Differential Operation
Low Power Consumption: 0.6W
4x4 QFN Package
3 Dividers-in-One
24 pin Quad Flat No Lead (QFN)
4x4 mm pkg, 0.5mm pad pitch
JEDEC MO-220 Compliant
Description
Marking Information:
UXC20P = Device Part Number
YYDD = Year & Work Week
XXXX = Reserved for future use
The UXC20P is a low noise programmable prescaler featuring either divide-by-2, divide-by-4, or divide-by-8
division ratios. The device features differential inputs and outputs, adjustable output swing and high input sen-
sitivity. The control inputs are CMOS and LVTTL compatible. The UXC20P is packaged in a 24 pin, 4mm x
4mm leadless surface mount package.
Application
The UXC20P can be used as a general purpose, fixed modulus prescaler in high frequency PLLs. The low
phase noise of the divider makes it ideal for generating low jitter, synchronous clocks in telecom applications.
Key Specifications (T=25 ºC)
Vee = -3.3V, Iee = 165mA, Zo = 50Ω
Parameter
Description
Minimum
Fin (GHz)
Pin (dBm)
Pout (dBm)
£(dBc/Hz)
Input Frequency
Nominal Input Power
Nominal Output Power
SSB Phase Noise @10kHz Offset
DC*
-10
-5
-
Pdc (mW)
DC Power Dissipation
-
Pspitback (dBm)
Freq/2 Power Spitback @Input
Pfundamental (dBm)
Fundamental Feedthru @Output
*Low frequency limit dependent on input edge speed
-
-
Typical
-
0
+5
-153
550
TBD
TBD
Maximum
20
+10
-
-
-
-
-
CENTELLAX • Web: http://www.centellax.com/ • Email: [email protected] • Tel: 866.522.6888 • Fax: 707.568.7647
Specifications subject to change without notice. Copyright © 2001-2006 Centellax, Inc. Printed in USA. 17 Aug 2006.
PAGE 1




UXC20P pdf, 반도체, 판매, 대치품
wwAw.pDaptalSicheaett4iUo.cnomNotes
Divider Mode
The UXC20P supports three division ratios controlled by two select lines which are compatible with
CMOS/LVTTL signaling levels. Table 1 lists the four states for the given logic levels on the SelA and SelB
select lines. For any of the three valid modes, circuitry which is not used is automatically powered down to
reduce power consumption.
Divider Outputs
The equivalent circuit of the divider outputs is shown on the below. The outputs require a DC return path
capable of handling ~35mA per side. If DC coupling is employed, the DC resistance of the receiving circuits
should be ~50 ohms (or less) to VCC to prevent excessive common mode voltage from saturating the
prescaler outputs. If AC coupling is used, the perfect embodiment is shown in figure 2. The discrete R/L/C ele-
ments should be resonance free up to the maximum frequency of operation for broadband applications.
The output amplitude can be adjusted over a 1.5:1 range by one of the two methods The Vadj pin voltage can
be set to VCC for maximum amplituded or VCC-1.3V for an amplitude ~2/3 the max swing. Voltages between
these two values will produce a linear change in output swing. Alternatively, users can use a 1k potentiometer
or fixed resistor tied between Vadj and VCC. Resistor values approaching 0 ohms will lead to the maximum
swing, while values approaching 1k will lead to the minimum output swing. Users who only need/want the
maximum swing should simply tie Vadj to VCC.
FIGURE 1:
Equivalent Circuit of Ouput Buffer
FIGURE 2:
Recommended Circuit for AC Coupled Outputs
Low Frequency Operation
Low frequency operation is limited by external bypass capacitors and the slew rate of the input clock. The next
paragraph shows the calculations for the bypass capacitors. If DC coupled, the device operates down to DC for
square-wave inputs. Sine-wave inputs are limited to ~50MHz due to the 10dBm max input power limitation.
The values of the coupling capacitors for the high-speed inputs and outputs (I/O’s) are determined by the low-
est frequency the IC will be operated at.
C>>
1
2.π.50Ω.f lowest
For example to use the device below 30kHz, coupling capacitors should be larger than 0.1uF.
CENTELLAX • Web: http://www.centellax.com/ • Email: [email protected] • Tel: 866.522.6888 • Fax: 707.568.7647
Specifications subject to change without notice. Copyright © 2001-2006 Centellax, Inc. Printed in USA. 17 Aug 2006.
PAGE 4

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UXC20P 전자부품, 판매, 대치품
wwNwe.DgaattaivSeheSeut4pUp.lcyom(DC Coupling)
Figure 5:
Biasing recommendations for negative supply with DC coupling applications
Negative Supply (AC Coupling)
Figure 6:
Biasing recommendations for negative supply with AC coupling applications
CENTELLAX • Web: http://www.centellax.com/ • Email: [email protected] • Tel: 866.522.6888 • Fax: 707.568.7647
Specifications subject to change without notice. Copyright © 2001-2006 Centellax, Inc. Printed in USA. 17 Aug 2006.
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UXC20P

DC-20GHz Programmable Binary Prescaler

Centellax
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