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55N03LT 데이터시트 PDF




NXP Semiconductors에서 제조한 전자 부품 55N03LT은 전자 산업 및 응용 분야에서
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부품번호 55N03LT 기능
기능 PHB55N03LT
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55N03LT 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Philips Semiconductors
N-channel TrenchMOStransistor
Logic level FET
Product specification
PHP55N03LT, PHB55N03LT
PHD55N03LT
FEATURES
’Trench’ technology
• Very low on-state resistance
• Fast switching
• Low thermal resistance
• Logic level compatible
SYMBOL
d
g
s
QUICK REFERENCE DATA
VDSS = 25 V
ID = 55 A
RDS(ON) 14 m(VGS = 10 V)
RDS(ON) 18 m(VGS = 5 V)
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.
Applications:-
• High frequency computer motherboard d.c. to d.c. converters
• High current switching
The PHP55N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB55N03LT is supplied in the SOT404 (D2PAK) surface mounting package.
The PHD55N03LT is supplied in the SOT428 (DPAK)surface mounting package.
PINNING
SOT78 (TO220AB) SOT404 (D2PAK)
PIN DESCRIPTION
1 gate
tab
tab
SOT428 (DPAK)
tab
2 drain 1
3 source
tab drain
1 23
2
13
2
13
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
VGSM
ID
IDM
Ptot
Tj, Tstg
Drain-source voltage
Drain-gate voltage
Gate-source voltage (DC)
Gate-source voltage (pulse
peak value)
Drain current (DC)
Drain current (pulse peak
value)
Total power dissipation
Operating junction and
storage temperature
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 k
Tj 150˚C
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
25
25
± 15
± 20
55
38
220
103
175
UNIT
V
V
V
V
A
A
A
W
˚C
1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.
October 1999
1
Rev 1.200




55N03LT pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
Philips Semiconductors
N-channel TrenchMOStransistor
Logic level FET
Product specification
PHP55N03LT, PHB55N03LT
PHD55N03LT
Drain Current, ID (A)
50
VGS = 10 V 5 V
45
4.5 V
Tj = 25 C
40
35
30 3 V
25
2.8 V
20
15 2.6 V
10
5
0
0
2.4 V
2.2 V
2V
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Drain-Source Voltage, VDS (V)
2
Fig.5. Typical output characteristics, Tj = 25 ˚C.
ID = f(VDS); parameter VGS
Drain-Source On Resistance, RDS(on) (Ohms)
0.1
2.2 V 2.4 V 2.6 V
2.8V
0.09
Tj = 25 C
0.08
3V
0.07
0.06
0.05
0.04
0.03
0.02 5 V VGS =4.5 V
0.01
0
0
10V
5 10 15 20 25 30 35 40 45 50
Drain Current, ID (A)
Fig.6. Typical on-state resistance, Tj = 25 ˚C.
RDS(ON) = f(ID); parameter VGS
Drain current, ID (A)
40
VDS > ID X RDS(ON)
35
30
25
20
15
10
175 C
5 Tj = 25 C
0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Gate-source voltage, VGS (V)
Fig.7. Typical transfer characteristics.
ID = f(VGS) ; conditions: VDS = 25 V; parameter Tj
Transconductance, gfs (S)
30
VDS > ID X RDS(ON)
25
Tj = 25 C
20
175 C
15
10
5
0
0 5 10 15 20 25 30 35 40
Drain current, ID (A)
Fig.8. Typical transconductance, Tj = 25 ˚C.
gfs = f(ID); conditions: VDS = 25 V
Normalised On-state Resistance
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)
Fig.9. Normalised drain-source on-state resistance.
a = RDS(ON)/RDS(ON)25 ˚C = f(Tj)
Threshold Voltage, VGS(TO) (V)
2.25
2
maximum
1.75
1.5
typical
1.25
1 minimum
0.75
0.5
0.25
0
-60 -40 -20
0
20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)
Fig.10. Gate threshold voltage.
VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
October 1999
4
Rev 1.200

4페이지










55N03LT 전자부품, 판매, 대치품
www.DataSheet4U.com
Philips Semiconductors
N-channel TrenchMOStransistor
Logic level FET
Product specification
PHP55N03LT, PHB55N03LT
PHD55N03LT
MECHANICAL DATA
Plastic single-ended surface mounted package (Philips version of D2-PAK); 3 leads
(one lead cropped)
SOT404
D1
D
HD
E
2
13
ee
b
A
A1
mounting
base
Lp
c
Q
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT A A1 b
c
D
max.
D1
mm 4.50 1.40 0.85 0.64 11 1.60
4.10 1.27 0.60 0.46
1.20
E
10.30
9.70
e
2.54
Lp HD Q
2.90 15.40 2.60
2.10 14.80 2.20
OUTLINE
VERSION
SOT404
IEC
REFERENCES
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
98-12-14
99-06-25
Fig.16. SOT404 surface mounting package. Centre pin connected to mounting base.
Notes
1. This product is supplied in anti-static packaging. The gate-source input must be protected against static
discharge during transport or handling.
2. Refer to SMD Footprint Design and Soldering Guidelines, Data Handbook SC18.
3. Epoxy meets UL94 V0 at 1/8".
October 1999
7
Rev 1.200

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