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29LV008BTC 데이터시트 PDF




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29LV008BTC 데이터시트, 핀배열, 회로
www.DataSheet4U.com
PRELIMINARY
MX29LV008T/B
8M-BIT [1M x 8] CMOS SINGLE VOLTAGE
3V ONLY FLASH MEMORY
FEATURES
• Extended single - supply voltage range 2.7V to 3.6V
• 1,048,576 x 8
• Single power supply operation
- 3.0V only operation for read, erase and program
operation
• Fast access time: 70/90ns
• Low power consumption
- 20mA maximum active current
- 0.2uA typical standby current
• Command register architecture
- Byte Programming (7us typical)
- Sector Erase (Sector structure 16K-Bytex1,
8K-Bytex2, 32K-Bytex1, and 64K-Byte x15)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
• Erase suspend/Erase Resume
- Suspends sector erase operation to read data from,
or program data to, any sector that is not being erased,
then resumes the erase.
• Status Reply
- Data polling & Toggle bit for detection of program and
erase operation completion.
• Ready/Busy pin (RY/BY)
- Provides a hardware method of detecting program or
erase operation completion.
• Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
- Tempoary sector unprotect allows code changes in
previously locked sectors.
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Low VCC write inhibit is equal to or less than 2.3V
• Package type:
- 40-pin TSOP
• Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
GENERAL DESCRIPTION
The MX29LV008T/B is a 8-mega bit Flash memory or-
ganized as 1M bytes of 8 bits. MXIC's Flash memories
offer the most cost-effective and reliable read/write non-
volatile random access memory. The MX29LV008T/B
is packaged in 40-pin TSOP. It is designed to be repro-
grammed and erased in system or in standard EPROM
programmers.
The standard MX29LV008T/B offers access time as fast
as 70ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the MX29LV008T/B has separate chip enable (CE) and
output enable (OE) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29LV008T/B uses a command register to manage
this functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29LV008T/B uses a 2.7V~3.6V VCC sup-
ply to perform the High Reliability Erase and auto Pro-
gram/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
P/N:PM0718
REV. 1.0, JUL. 31, 2001
1




29LV008BTC pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
MX29LV008T/B
Table 2: MX29LV008B SECTOR ARCHITECTURE
Sector
Sector Size
Address range
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
16Kbytes
8Kbytes
8Kbytes
32Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64Kbytes
64kbytes
00000h-03FFFh
04000h-05FFFh
06000h-07FFFh
08000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
40000h-4FFFFh
50000h-5FFFFh
60000h-6FFFFh
70000h-7FFFFh
80000h-8FFFFh
90000h-9FFFFh
A0000h-AFFFFh
B0000h-BFFFFh
C0000h-CFFFFh
D0000h-DFFFFh
E0000h-EFFFFh
F0000h-FFFFFh
Sector Address
A19 A18 A17 A16 A15 A14 A13
000000 X
000001 0
000001 1
00001X X
0 0 0 1XX X
0 0 1 0XX X
0 0 1 1XX X
0 1 0 0XX X
0 1 0 1XX X
0 1 1 0XX X
0 1 1 1XX X
10 0 0XX X
10 0 1XX X
1 0 1 0XX X
1 0 1 1XX X
11 0 0XX X
1 1 0 1XX X
1 1 1 0XX X
1 1 1 1XX X
P/N:PM0718
REV. 1.0, JUL. 31, 2001
4

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MX29LV008T/B
lect command through the command register without
requiring VID, as shown in table4.
To verify whether or not sector being protected, the sec-
tor address must appear on the appropriate highest or-
der address bit (see Table 1 and Table 2). The rest of
address bits, as shown in table3, are don't care. Once
all necessary bits have been set as required, the pro-
gramming equipment may read the corresponding iden-
tifier code on Q7~Q0.
TABLE 3. MX29LV008T/B AUTO SELECT MODE OPERATION
Description
Read Silicon ID
Manfacturer Code
Read Silicon ID
(Top Boot Block)
Device ID
(Bottom Boot Block)
A19 A12 A9 A8 A6 A5 A1 A0
CE OE WE
|
|
|
|
A13 A10
A7
A2
L L H X X VID X L X L L
L L H X X VID X L X L H
L L H X X VID X L X L H
Sector Protection
Verification
L L H SA X VID X L X H L
NOTE:SA=Sector Address, X=Don't Care, L=Logic Low, H=Logic High
Q7~Q0
C2H
3EH
37H
01H
(protected)
00H
(unprotected)
P/N:PM0718
REV. 1.0, JUL. 31, 2001
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