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PDF MC33780 Data sheet ( Hoja de datos )
| Número de pieza | MC33780 | |
| Descripción | Dual DBUS Master | |
| Fabricantes | Freescale Semiconductor | |
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www.DFatraSeheesetc4Ua.lceomSemiconductor
Technical Data
Document order number: MC33780
Rev 3.0, 5/2006
Dual DBUS Master with
Differential Drive and
Frequency Spreading
The 33780 is a master device for two differential DBUS buses. It
contains the logic to interface the buses to a standard serial
peripheral interface (SPI) port and the analog circuitry to drive data
and power over the bus as well as receive data from the remote slave
devices.
The differential mode of the 33780 generates lower electro-
magnetic interference (EMI) in situations where data rates and wiring
make this a problem. Frequency spreading further reduces in-
terference by spreading the energy across many channels, reducing
the energy in any single channel.
Features
• Two Independent DBUS I/Os
• Common SPI Interface for All Operations
• Open-Drain Interrupt Output with Pull-up
• Maskable Interrupts for Send and Receive Data Status
• Automatic Message Cyclical Redundancy Checking (CRC)
Generation and Checking
• Four-Stage Transmit and Receive Buffers
• 8- to 16-Bit Messages with 0- to 8-Bit CRC
• Independent Frequency Spreading for Each Channel
• Pb-Free Packaging Designated by Suffix Code EG
33780
DIFFERENTIAL DBUS MASTER
EG (Pb-FREE SUFFIX)
98ASB42567B
16-TERMINAL SOICW
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
MC33780EG/R2 -40°C to 85°C
16 SOICW
+5.0 V
+25 V
MCU
VCC
SCLK
CS
MOSI
MISO
RST
INT
CLK
GND
33780
VCC VSUP
SCLK
CS
MOSI
MISO
D0H
D0L
RST
INT
D1H
D1L
CLK
GND
DSI/DBUS SLAVE
Twisted Pair
33793
DSI/DBUS SLAVE
33793
4.7 nF capacitors from D0H, D0L, D1H
and D1L to circuit ground are required
for proper operation.
Figure 1. 33780 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2006. All rights reserved.
1 page  
www.DataSheet4U.com
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 4.75 V ≤ VCC ≤ 5.25 V, 9.0 V ≤ VSUP ≤ 25 V,-40°C ≤ TA ≤ 85°C unless otherwise
noted. Voltages relative to GND unless otherwise noted. Typical values noted reflect the approximate parameter means at
TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol Min Typ Max Unit
POWER INPUT REQUIREMENTS (VSUP, VCC)
IVSUP Supply Current (| IBUS | ≤ 10 µA) (Test Mode, CLK = 4.0 MHz)
Idle, HiZ
Signal High, Signal Low
IVCC Supply Current (Test Mode, CLK = 4.0 MHz)
Signal High, Signal Low
MICROCONTROLLER INTERFACE (RST, CS, MOSI, SCLK, AND CLK)
IVSUP
IVCC
mA
– 6.5 10
– 15 23
mA
– 4.5 6.0
I/O Logic Levels (RST, CS, MOSI, SCLK, and CLK)
Input High
Input Low
Input Hysteresis (2)
Input Capacitance (2)
RST, CS, MOSI, SCLK, and CLK
Output Low Voltage
MISO and INT Terminals = 0.3 mA
Output High Voltage
MISO Terminal = -0.3 mA
Output Leakage Current
MISO Terminal = 0 V
MISO Terminal = VCC
INT Pullup Current
VOUT = VCC - 1.0 V
SCLK, CS Pullup Current
VOUT = VCC - 1.0 V
RST Pulldown Current
VOUT = 1.0 V
CLK, MOSI Pulldown Current
VOUT = 1.0 V
BUS TRANSMITTER (D0H, D0L, D1H, D1L)
Output Bus Idle Voltage (Differential)
InH = -200 mA, InL = 200 mA (3)
Output Signal High Voltage (Differential)
-12.5 mA ≤ InH ≤ 1.0 mA, -1.0 mA ≤ InL ≤ 12.5 mA (3)
Output Signal Low Voltage (Differential)
-12.5 mA ≤ InH ≤ 1.0 mA, -1.0 mA ≤ InL ≤ 12.5 mA (3)
Notes
2. Not measured in production.
3. InH = bus current at DnH, InL = bus current at DnL.
4. VDnD = VDnH - VDnL.
VIH
VIL
VHYST
CI
VOL
VOH
IMISO
IINTPU
IPU
IRSTPD
IPD
0.7 –
––
– 500
– 10
0–
VCC - 0.8
-10
-10
–
–
–
-100
-75
-20 -10
4.0 7.0
5.0 10
VDnD(IDLE) (4)
VDnD(HIGH) (4)
VDnD(LOW) (4)
VSUP - 2.5
4.175
1.175
–
4.5
1.5
–
0.3
–
20
0.8
VCC
10
10
-50
-5.0
10
20
–
4.825
1.825
VCC
VCC
mV
pF
V
V
µA
µA
µA
µA
µA
V
V
V
Analog Integrated Circuit Device Data
Freescale Semiconductor
33780
5
5 Page 
www.DataSheet4U.com
DnH VSUP
Vmid + 2.25 V
Vmid + 0.75 V
Vmid
Vmid - 0.75 V
Vmid - 2.25 V
DnL
0V
DnH VSUP
Overvoltage
Threshold
Vmid + 2.25 V
Vmid + 0.75 V
Vmid (Clamped)
Vmid - 0.75 V
Figure 5. DBUS Normal Bus Waveforms
Vmid - 2.25 V
DnL
0V
Figure 6. DBUS Overvoltage Bus Waveforms
Analog Integrated Circuit Device Data
Freescale Semiconductor
TIMING DIAGRAMS
33780
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MC33780.PDF ] | |
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