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부품번호 ML145162 기능
기능 60 MHz and 85 MHz Universal Programmable Dual PLL Frequency Synthesizers CMOS
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ML145162 데이터시트, 핀배열, 회로
www.DataSheet4U.com
ML145162
60 MHz and 85 MHz Universal
Programmable Dual PLL Frequency
Synthesizers
CMOS
Legacy Device: Motorola MC145162
The ML145162 is a dual phase–locked loop (PLL) frequency synthesizer
especially designed for CT–1 cordless phone applications worldwide. This
frequency synthesizer is also for any product with a frequency operation at
60MHz or below.
The device features fully programmable receive, transmit, reference, and
auxiliary reference counters accessed through an MCU serial interface. This
feature allows this device to operate in any CT–1 cordless phone application.
The device consists of two independent phase detectors for transmit and
receive loops. A common reference oscillator, driving two independent refer-
ence frequency counters, provides independent reference frequencies for
transmit and receive loops. The auxiliary reference counter allows the user to
select an additional reference frequency for receive and transmit loops if
required.
• Operating Voltage Range: 2.5 to 5.5 V
• Operating Temperature Range: TA = – 40 to +75°C
• Operating Power Consumption: 3.0 mA @ 2.5 V
• Maximum Operating Frequency: 60 MHz @ 200 mV p–p, VDD = 2.5 V
• Three or Four Pins Used for Serial MCU Interface
• Built–In MCU Clock Output with Frequency of Reference Oscillator ÷3/÷4
• Power Saving Mode Controlled by MCU
• Lock Detect Signal
• On–Chip Reference Oscillator Supports External Crystals to 16.0 MHz
• Reference Frequency Counter Division Range: 16 to 4095
• Auxiliary Reference Frequency Counter Division Range: 16 to 16,383
• Transmit Counter Division Range: 16 to 65,535
• Receive Counter Division Range: 16 to 65,535
16
1
P DIP 16 = EP
PLASTIC DIP
CASE 648
16
1
SOG 16 = -5P
SOG PACKAGE
CASE 751B
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
P DIP 16
SOG 16
MC145162P ML145162EP
MC145162D ML145162-5P
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
PIN ASSIGNMENT
CLK
ADin
Din
ENB
MCUCLK
VSS
OSCin
OSCout
1
2
3
4
5
6
7
8
16 LD
15 TxPDout
14 fin–T
13 TxPS/fTx
12 VDD
11 RxPS/FRx
10 RxPDout
9 fin–R
Page 1 of 24
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ML145162 pdf, 반도체, 판매, 대치품
ML145162
www.DataSheet4U.com
LANSDALE Semiconductor, Inc.
SWITCHING CHARACTERISTICS (TA = 25°C, CL = 50 pF)
Symbol
tTLH
Characteristic
Output Rise Time
Figure
No.
1
tTHL
Output Fall Time
1
tr, tf Input Rise and Fall Time
OSCin
2
tw Input Pulse Width
CLK and ENB
3
fmax
tst
tsu
th
Input Frequency
Input = Sine Wave @ 200 mV p–p
Minimum Start–Up Time
Setup Time
Hold Time
OSCin
fin–R, fin–T
DATA to CLK
ENB to CLK
CLK to DATA
5
5
trec Recovery Time
ENB to CLK
5
tsu1
th1
f
fMCUCLK
Setup Time
Hold Time
Phase Detector Frequency
Output Clock Frequency
(OSCin 3)
ENB to CLK
CLK to ENB
MCUCLK
4
4
VDD
2.5
5.5
2.5
5.5
2.5
5.5
2.5
5.5
2.5 – 5.5
2.5 – 5.5
2.5
5.5
3.0
5.0
3.0
5.0
2.5 – 5.5
2.5 – 5.5
Guaranteed Limit
Min Max
— 200
— 100
— 200
— 100
— 5.0
— 4.0
80 —
60 —
— 16
— 60
10
100 —
200 —
80 —
40 —
80 —
40 —
80 —
600 —
dc 12.5
dc 5.33
Unit
ns
ns
µs
ns
MHz
ms
ns
ns
ns
ns
ns
kHz
MHz
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ML145162 전자부품, 판매, 대치품
ML145162
www.DataSheet4U.com
LANSDALE Semiconductor, Inc.
fR, REFERENCE
(OSCin REFERENCE COUNTER)
fV, FEEDBACK
(fin–T Tx COUNTER OR
fin–R Rx COUNTER)
TxPDout
OR
RxPDout
LD
VH
VL
VH
VL
* VH
HIGH IMPEDANCE
VH = High voltage level.
VL = Low voltage level.
*At this point, when both fR and fV are in phase, the output is forced to near mid supply.
NOTE: The TxPDout and RxPDout generate error pulses during out–of–lock conditions. When locked in phase and fre-
quency, the output is high impedance and the voltage at that pin is determined by the low–pass filter capacitor.
Figure 7. Phase Detector/Lock Detector Output Waveforms
MCU PROGRAMMING SCHEME
The MCU programming scheme is defined in two formats
controlled by the ENB input. If the enable signal is high during
the serial data transfer, control register/reference frequency
programming is selected. If the ENB is low, programming of
the transmit and receive counters is selected. During program-
ming of the transmit and receive counters, both ADin and Din
pins can input the data to the transmit and receive counters.
Both counters’ data is clocked into the PLL internal shift regis-
ter at the leading edge of the CLK signal. It is not necessary to
reprogram the reference frequency counter/control register
when using the enable signal to program the transmit/receive
channels.
In programming the control register/reference frequency
scheme, the most significant bit (MSB) of the programming
word identifies whether the input data is the control word or
the reference frequency data word. If the MSB is 1, the input
data is the control word (Figure 8). Also see Figure 8 and Table
1 for control register and bit function. If the MSB is 0, the
input data is the reference frequency (Figure 9).
The reference frequency data word is a 32–bit word contain-
ing the 12–bit reference frequency data, the 14–bit auxiliary
reference frequency counter information, the reference fre-
quency selection plus, the auxiliary reference frequency count-
er enable bit (Figure 9).
If the AUX REF ENB bit is high, the 14–bit auxiliary refer-
ence frequency counter provides an additional phase reference
frequency output for the loops. If AUX REF ENB bit is low,
the auxiliary reference frequency counter is forced into
power–down mode for current saving. (Other power down
modes are also provided through the control register per Table
2 and Figure 8.) At the falling edge of the ENB signal, the data
is stored in the registers.
There are two interfacing schemes for the universal channel
mode: the three–pin and the four–pin interfacing schemes. The
three–pin interfacing scheme is suited for use with the MCU
SPI (serial peripheral interface) (Figure 10), while the four–pin
interfacing scheme is commonly used for general I/O port con-
nection (Figure 11).
For the three–pin interfacing scheme, the auxiliary data
select bit is set to 0. All 32 bits of data, which define both
the16–bit transmit counter and the 16–bit receive counter, latch
into the PLL internal register through the data in pins at the
leading edge of CLK. See Figures 12 and 13.
For the four–pin interfacing scheme, the auxiliary data select
bit is set to 1. In this scheme, the 16–bit transmit counter’s data
enters into the ADin pin at the same time as the 16–bit receive
counter’s data enters into the Din pin. This simultaneous entry
of the transmit and receive counters causes the programming
period of the four–pin scheme to be half that of the three–pin
scheme (see Figures 14 and 15).
While programming Tx/Rx Channel Counter, the ENB pin
must be pulsed to provide falling edge to latch the shifted data
after the rising edge of the last clock. Maximum data transfer
rate is 500 kbps.
NOTE
10 ms should be allowed for initial start–up time for
the oscillator to allow all registers to clear and enable
programming of new register values.
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부품번호상세설명 및 기능제조사
ML145162

60 MHz and 85 MHz Universal Programmable Dual PLL Frequency Synthesizers CMOS

LANSDALE Semiconductor
LANSDALE Semiconductor

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