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부품번호 ML145564 기능
기능 (ML145554 - ML145567) PCM Codec-Filter
제조업체 LANSDALE Semiconductor
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ML145564 데이터시트, 핀배열, 회로
www.DataSheet4U.com
ML145554 ML145564
ML145557 ML145567
PCM Codec–Filter
Legacy Device: Motorola MC145554, MC145557, MC145564, MC145567
The ML145554, ML145557, ML145564, and ML145567 are all per channel
PCM Codec–Filters. These devices perform the voice digitization and recon-
struction as well as the band limiting and smoothing required for PCM sys-
tems. They are designed to operate in both synchronous and asynchronous
applications and contain an on–chip precision voltage reference. The
ML145554 (Mu–Law) and ML145557 (A–Law) are general purpose devices
that are offered in 16–pin packages. The ML145564 (Mu–Law) and
ML145567 (A–Law), offered in 20–pin packages, add the capability of analog
loopback and push–pull power amplifiers with adjustable gain.
These devices have an input operational amplifier whose output is the input
to the encoder section. The encoder section immediately low–pass filters the
analog signal with an active R–C filter to eliminate very–high–frequency noise
from being modulated down to the pass band by the switched capacitor filter.
From the active R–C filter, the analog signal is converted to a differential sig-
nal. From this point, all analog signal processing is done differentially. This
allows processing of an analog signal that is twice the amplitude allowed by a
single–ended design, which reduces the significance of noise to both the invert-
ed and non–inverted signal paths. Another advantage of this differential design
is that noise injected via the power supplies is a common–mode signal that is
cancelled when the inverted and non–inverted signals are recombined. This
dramatically improves the power supply rejection ratio.
After the differential converter, a differential switched capacitor filter band-
passes the analog signal from 200 Hz to 3400 Hz before the signal is digitized-
by the differential compressing A/D converter.
The decoder accepts PCM data and expands it using a differential D/A con-
verter. The output of the D/A is low–pass filtered at 3400 Hz and sinX/X com-
pensated by a differential switched capacitor filter. The signal is then filtered
by an active R–C filter to eliminate the out–of–band energy of the switched
capacitor filter.
These PCM Codec–Filters accept both long–frame and short–frame industry
standard clock formats. They also maintain compatibility with Motorola’s fami-
ly of TSACs and MC3419/MC34120 SLIC products.
The ML145554/57/64/67 family of PCM Codec–Filters utilizes CMOS due
to its reliable low–power performance and proven capability for complex
analog/digital VLSI functions.
FEATURES
16
1
16
1
P DIP 16 = EP
PLASTIC DIP
CASE 648
ML145554/57
SOG 16 = -5P
SOG PACKAGE
CASE 751G
ML145554/57
20
1
20
1
P DIP 20 = RP
PLASTIC DIP
CASE 738
ML145564/67
SOG 20 = -6P
SOG PACKAGE
CASE 751D
ML145564/67
CROSS REFERENCE/ORDERING INFORMATION
PACKAGE
MOTOROLA
LANSDALE
P DIP 16
SO 16W
P DIP 16
SO 16W
P DIP 20
SO 20W
P DIP 20
SO 20W
MC145554P
MC145554DW
MC145557P
MC145557DW
MC145564P
MC145564DW
MC145567P
MC145567DW
ML145554EP
ML145554-5P
ML145557EP
ML145557-5P
ML145564RP
ML145564-6P
ML145567RP
ML145567-6P
Note: Lansdale lead free (Pb) product, as it
becomes available, will be identified by a part
number prefix change from ML to MLE.
ML145554/57(16–Pin Package)
• Fully Differential Analog Circuit Design for Lowest Noise
• Performance Specified for Extended Temperature Range of – 40 to + 85°C
• Transmit Band–Pass and Receive Low–Pass Filters On–Chip
• Active R–C Pre–Filtering and Post–Filtering
• Mu–Law Companding ML145554
• A–Law Companding ML145557
• On–Chip Precision Voltage Reference (2.5 V)
• Typical Power Dissipation of 40 mW, Power Down of 1.0 mW at ±5 V
ML145564/67(20–Pin Package) — All of the Features of the ML145554/57 Plus:
• Mu–Law Companding ML145564
• A–Law Companding ML145567
• Push–Pull Power Drivers with External Gain Adjust
• Analog Loopback
Page 1 of 18
www.lansdale.com
Issue A




ML145564 pdf, 반도체, 판매, 대치품
ML145554, ML145557, ML145564, ML145567
www.DataSheet4U.com
LANSDALE Semiconductor, Inc.
serial PCM word, clocked by BCLKX, out of DX. If the FSX
pulse is high for more than eight BCLKX periods, the DX and
TSX outputs will remain in a low–impedance state until FSX is
brought low. The length of the FSX pulse is used to determine
whether the transmit and receive digital I/O conforms to the
Short Frame Sync or to the Long Frame Sync convention.
TSX
Transmit Time Slot Indicator
This is an open–drain output that goes low whenever the DX
output is in a low–impedance state (i.e., during the transmit
time slot when the PCM word is being output) for enabling a
PCM bus driver.
ANLB
Analog Loopback Control Input (ML145564/67 Only)
When held high, this pin causes the input of the transmit RC
active filter to be disconnected from GSX and connected to
VPO+ for analog loopback testing. This pin is held low in
normal operation.
ANALOG
GSX
Gain–Setting Transmit
This output of the transmit gain–adjust operational amplifi-
er is internally connected to the encoder section of the device.
It must be used in conjunction with VFXI– and VFXI+ to set
the transmit gain for a maximum signal amplitude of 2.5 V
peak. This output can drive a 600 load to 2.5 V peak.
VFXI–
Voice–Frequency Transmit Input (Inverting)
This is the inverting input of the transmit gain–adjust
operational amplifier.
VFXI+
Voice–Frequency Transmit Input (Non–Inverting)
This is the non–inverting input of the transmit gain–adjust
operational amplifier.
VFRO
Voice–Frequency Receive Output
This receive analog output is capable of driving a 600 load
to 2.5 V peak.
VPI
Voltage Power Input (ML145564/67 Only)
This is the inverting input to the first receive power ampli-
fier. Both of the receive power amplifiers can be powered
down by connecting this input to VBB.
VPO–
Voltage Power Output (Inverted) (ML145564/67 Only)
This inverted output of the receive push–pull power ampli-
fiers can drive 300 to 3.3 V peak.
VPO+
Voltage Power Output (Non–Inverted) (ML145554/67 Only)
This non–inverted output of the receive push–pull power
amplifier pair can drive 300 to 3.3 V peak.
POWER SUPPLY
GNDA
Analog Ground
This terminal is the reference level for all signals, both ana-
log and digital. It is 0 V.
VCC
Positive Power Supply
VCC is typically 5 V.
VBB
Negative Power Supply
VBB is typically – 5 V.
FUNCTIONAL DESCRIPTION
ANALOG INTERFACE AND SIGNAL PATH
The transmit portion of these codec–filters includes a
low–noise gain setting amplifier capable of driving a 600
load. Its output is fed to a three–pole anti–aliasing pre–filter.
This pre–filter incorporates a two–pole Butterworth active
low–pass filter, and a single passive pole. This pre–filter is
followed by a single ended–to–differential converter that is
clocked at 256 kHz. All subsequent analog processing uti-
lizes fully differential circuitry. The next section is a
fully–differential, five–pole switched capacitor low–pass fil-
ter with a 3.4 kHz passband. After this filter is a 3–pole
switched–capacitor high–pass filter having a cutoff frequen-
cy of about 200 Hz. This high–pass stage has a transmission
zero at DC that eliminates any DC coming from the analog
input or from accumulated operational amplifier offsets in
the preceding filter stages. The last stage of the high–pass
filter is an autozeroed sample and hold amplifier.
One bandgap voltage reference generator and
digital–to–analog converter (DAC) are shared by the transmit
and receive sections. The autozeroed, switched–capacitor
bandgap reference generates precise positive and negative
reference voltages that are independent of temperature and
power supply voltage. A binary–weighted capacitor array
(CDAC) forms the chords of the companding structure,
while a resistor string (RDAC) implements the linear steps
within each chord. The encode process uses the DAC, the
voltage reference, and a frame–by–frame autozeroed com-
parator to implement a successive–approximation conversion
algorithm. All of the analog circuitry involved in the data
conversion the voltage reference, RDAC, CDAC, and com-
parator are implemented with a differential architecture.
The receive section includes the DAC described above,
asample and hold amplifier, a five–pole 3400 Hz switched-
capacitor low–pass filter with sinX/X correction, and a
two–pole active smoothing filter to reduce the spectral com-
ponents of the switched capacitor filter. The output of the
smoothing filter is a power amplifier that is capable of driv-
ing a 600 load. The ML145564 and ML145567 add a pair
of power amplifiers that are connected in a push–pull con-
figuration; two external resistors set the gain of both of the
Page 4 of 18
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Issue A

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ML145564 전자부품, 판매, 대치품
LANSDALE Semiconductor, Inc.
www.DataSheet4U.com
ML145554, ML145557, ML145564, ML145567
ANALOG ELECTRICAL CHARACTERISTICS
(VCC = + 5 V ± 5%, VBB = – 5 V ± 5%, VFXI – Connected to GSX, TA = – 40 to + 85°C)
Characteristic
Input Current (– 2.5 Vin + 2.5 V)
VFXI +, VFXI –
AC Input Impedance to GNDA (1 kHz)
VFXI +, VFXI –
Input Capacitance
VFXI +, VFXI –
Input Offset Voltage of GSX Op Amp
VFXI +, VFXI –
Input Common Mode Voltage Range
VFXI +, VFXI –
Input Common Mode Rejection Ratio
VFXI +, VFXI –
Unity Gain Bandwidth of GSX Op Amp (Rload 10 k)
DC Open Loop Gain of GSX Op Amp (Rload 10 k)
Equivalent Input Noise (C–Message) Between VFXI+ and VFXI– at GSX
Output Load Capacitance for GSX Op Amp
Output Voltage Range for GSX
Rload = 10 kto GNDA
Rload = 600 to GNDA
Output Current (– 2.8 V Vout + 2.8 V)
GSX, VFRO
Output Impedance VFRO (0 to 3.4 kHz)
Output Load Capacitance for VFRO
VFRO Output DC Offset Voltage Referenced to GNDA
Transmit Power Supply Rejection
Positive, 0 to 100 kHz, C–Message
Negative, 0 to 100 kHz, C–Message
Receive Power Supply Rejection
Positive, 0 to 100 kHz, C–Message
Positive, 4 kHz to 25 kHz
Positive, 25 kHz to 50 kHz
Negative, 0 to 100 kHz, C–Message
Negative, 4 kHz to 25 kHz
Negative, 25 kHz to 50 kHz
ML145564/67 Power Drivers
Input Current (– 1 V VPI + 1 V)
VPI
Input Resistance (– 1 V VPI + 1 V)
VPI
Input Offset Voltage (VPI Connected to VPO–)
VPI
Output Resistance, Inverted Unity Gain
VPO+ or VPO–
Unity Gain Bandwidth, Open Loop
VPO–
Load Capacitance (∞ Ω ≥ Rload 300 )
VPO+ or VPO– to GNDA
Gain from VPO– to VPO+ (Rload = 300 , VPO+ to GNDA Level at VPO–
= 1.77 Vrms, +3 dBm0)
Maximum 0 dBm0 Level for Better than 0.1 dB Linearity Over the
Range – 10 dBm0 to + 3 dBm0 (For Rload between VPO+
and VPO–)
Power Supply Rejection of VCC or VBB (VPO– Connected to VPI)
VPO + or VPO – to GNDA
Rload = 600
Rload = 1200
Rload = 10 k
0 to 4 kHz
4 to 50 kHz
Differential Power Supply Rejection of VCC or VBB (VPO– Connected to VPI)
VPO+ to VPO–, 0 to 50 kHz
Min
10
– 2.5
75
0
– 3.5
– 2.8
± 5.0
0
45
45
50
50
43
50
45
38
5
0
3.3
3.5
4.0
55
35
50
Typ
± 0.05
20
65
1000
– 20
1
± 0.05
10
1
400
–1
Max
± 0.2
10
± 25
2.5
100
+ 3.5
+ 2.8
500
± 100
Unit
µA
M
pF
mV
V
dB
kHz
dB
dBrnC0
pF
V
mA
pF
mV
dBC
dBC
dB
dB
dBC
dB
dB
± 0.5
± 50
1000
µA
M
mV
kHz
pF
V/V
Vrms
dB
dB
Page 7 of 18
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관련 데이터시트

부품번호상세설명 및 기능제조사
ML145564

(ML145554 - ML145567) PCM Codec-Filter

LANSDALE Semiconductor
LANSDALE Semiconductor
ML145567

(ML145554 - ML145567) PCM Codec-Filter

LANSDALE Semiconductor
LANSDALE Semiconductor

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