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ADC0803 데이터시트 PDF




Harris에서 제조한 전자 부품 ADC0803은 전자 산업 및 응용 분야에서
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부품번호 ADC0803 기능
기능 (ADC0802 - ADC0804) 8-Bit/ Microprocessor- Compatible/ A/D Converters
제조업체 Harris
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ADC0803 데이터시트, 핀배열, 회로
www.DataSheet4U.com
Semiconductor
August 1997
ADC0802, ADC0803
ADC0804
8-Bit, Microprocessor-
Compatible, A/D Converters
Features
Description
• 80C48 and 80C80/85 Bus Compatible - No Interfacing
Logic Required
• Conversion Time < 100µs
• Easy Interface to Most Microprocessors
• Will Operate in a “Stand Alone” Mode
• Differential Analog Voltage Inputs
• Works with Bandgap Voltage References
• TTL Compatible Inputs and Outputs
• On-Chip Clock Generator
• 0V to 5V Analog Voltage Input Range (Single + 5V Supply)
• No Zero-Adjust Required
The ADC0802 family are CMOS 8-Bit, successive-approxi-
mation A/D converters which use a modified potentiometric
ladder and are designed to operate with the 8080A control
bus via three-state outputs. These converters appear to the
processor as memory locations or I/O ports, and hence no
interfacing logic is required.
The differential analog voltage input has good common-
mode-rejection and permits offsetting the analog zero-input-
voltage value. In addition, the voltage reference input can be
adjusted to allow encoding any smaller analog voltage span
to the full 8 bits of resolution.
Ordering Information
PART NUMBER
ADC0802LCN
ADC0802LCD
ADC0802LD
ADC0803LCN
ADC0803LCD
ADC0803LCWM
ADC0803LD
ADC0804LCN
ADC0804LCD
ADC0804LCWM
ERROR
±1/2 LSB
±3/4 LSB
±1 LSB
±1/2 LSB
±3/4 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
EXTERNAL CONDITIONS
VREF/2 = 2.500VDC (No Adjustments)
VREF/2 Adjusted for Correct Full Scale
Reading
VREF/2 = 2.500VDC (No Adjustments)
TEMP. RANGE (oC)
PACKAGE
0 to 70
20 Ld PDIP
-40 to 85
20 Ld CERDIP
-55 to 125
20 Ld CERDIP
0 to 70
20 Ld PDIP
-40 to 85
20 Ld CERDIP
-40 to 85
20 Ld SOIC
-55 to 125
20 Ld CERDIP
0 to 70
20 Ld PDIP
-40 to 85
20 Ld CERDIP
-40 to 85
20 Ld SOIC
PKG. NO
E20.3
F20.3
F20.3
E20.3
F20.3
M20.3
F20.3
E20.3
F20.3
M20.3
Pinout
Typical Application Schematic
ADC0802, ADC0803, ADC0804
(PDIP, CERDIP)
TOP VIEW
CS 1
RD 2
WR 3
CLK IN 4
INTR 5
VIN (+) 6
VIN (-) 7
AGND 8
VREF/2 9
DGND 10
20 V+ OR VREF
19 CLK R
18 DB0 (LSB)
17 DB1
16 DB2
15 DB3
14 DB4
13 DB5
12 DB6
11 DB7 (MSB)
ANY
µPROCESSOR
1 CS
2 RD
V+ 20
CLK R 19
+5V 150pF
3 WR CLK IN 4 10K
5 INTR
11 DB7
12 DB6
13 DB5
14 DB4
15 DB3
16 DB2
17 DB1
18 DB0
VIN (+)
VIN (-)
AGND
VREF/2
DGND
6
7
8
9
10
DIFF
INPUTS
VREF/2
8-BIT RESOLUTION
OVER ANY
DESIRED
ANALOG INPUT
VOLTAGE RANGE
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1997
6-5
File Number 3094.1




ADC0803 pdf, 반도체, 판매, 대치품
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ADC0802, ADC0803, ADC0804
Electrical Specifications (Notes 1, 7) (Continued)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
CONVERTER SPECIFICATIONS V+ = 5V, -55oC to 125oC and fCLK = 640kHz, Unless Otherwise Specified
Total Unadjusted Error
ADC0802
VREF/2 = 2.500V
- - ±1
ADC0803
VREF/2 Adjusted for Correct Full
Scale Reading
-
- ±1
VREF/2 Input Resistance
Analog Input Voltage Range
Input Resistance at Pin 9
(Note 2)
1.0
GND-0.05
DC Common-Mode Rejection
Over Analog Input Voltage Range
-
Power Supply Sensitivity
V+ = 5V ±10% Over Allowed Input
Voltage Range
-
AC TIMING SPECIFICATIONS V+ = 5V, and TA = 25oC, Unless Otherwise Specified
Clock Frequency, fCLK
V+ = 6V (Note 3)
100
V+ = 5V
100
1.3
-
±1/8
±1/8
640
640
-
(V+) + 0.05
±1/4
±1/4
1280
800
Clock Periods per Conversion
(Note 4), tCONV
62 - 73
Conversion Rate In Free-Running INTR tied to WR with CS = 0V,
Mode, CR
fCLK = 640kHz
-
- 8888
Width of WR Input (Start Pulse
Width), tW(WR)I
CS = 0V (Note 5)
100 -
-
Access Time (Delay from Falling CL = 100pF (Use Bus Driver IC for
Edge of RD to Output Data Valid), Larger CL)
tACC
-
135 200
Three-State Control (Delay from CL = 10pF, RL= 10K
Rising Edge of RD to Hl-Z State), (See Three-State Test Circuits)
t1H, t0H
-
125 250
Delay from Falling Edge of WR to
Reset of INTR, tWI, tRI
- 300 450
Input Capacitance of Logic
Control Inputs, CIN
-5-
Three-State Output Capacitance
(Data Buffers), COUT
-5-
DC DIGITAL LEVELS AND DC SPECIFICATIONS V+ = 5V, and TMIN to TMAX, Unless Otherwise Specified
CONTROL INPUTS (Note 6)
Logic “1“ Input Voltage (Except
Pin 4 CLK IN), VINH
Logic “0“ Input Voltage (Except
Pin 4 CLK IN), VINL
CLK IN (Pin 4) Positive Going
Threshold Voltage, V+CLK
CLK IN (Pin 4) Negative Going
Threshold Voltage, V-CLK
CLK IN (Pin 4) Hysteresis, VH
Logic “1” Input Current
(All Inputs), IINHI
Logic “0” Input Current
(All Inputs), IINLO
Supply Current (Includes Ladder
Current), I+
V+ = 5.25V
V+ = 4.75V
VlN = 5V
VlN = 0V
fCLK = 640kHz,TA = 25oC
and CS = Hl
2.0 - V+
- - 0.8
2.7 3.1 3.5
1.5 1.8 2.1
0.6 1.3 2.0
- 0.005 1
-1 -0.005
-
- 1.3 2.5
DATA OUTPUTS AND INTR
Logic “0” Output Voltage, VOL
lO = 1.6mA, V+ = 4.75V
- - 0.4
UNITS
LSB
LSB
k
V
LSB
LSB
kHz
kHz
Clocks/Conv
Conv/s
ns
ns
ns
ns
pF
pF
V
V
V
V
V
µΑ
µA
mA
V
6-8

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ADC0803 전자부품, 판매, 대치품
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ADC0802, ADC0803, ADC0804
Typical Performance Curves (Continued)
8
V+ = 5V
7
DATA OUTPUT
BUFFERS
6
5 ISOURCE
VOUT = 2.4V
4
3
2
-50
-ISINK
VOUT = 0.4V
-25
0
25 50
75 100
TA AMBIENT TEMPERATURE (oC)
125
FIGURE 8. OUTPUT CURRENT vs TEMPERATURE
Timing Diagrams
1.6
fCLK = 640kHz
1.5
V+ = 5.5V
1.4
1.3
V+ = 5.0V
1.2
1.1 V+ = 4.5V
1.0
-50
-25 0 25 50 75 100
TA AMBIENT TEMPERATURE (oC)
125
FIGURE 9. POWER SUPPLY CURRENT vs TEMPERATURE
CS
WR
ACTUAL INTERNAL
STATUS OF THE
CONVERTER
tWI
tW(WR)I
(LAST DATA READ)
INTR
(LAST DATA NOT READ)
“BUSY”
“NOT BUSY”
1 TO 8 x 1/fCLK
INTERNAL TC
tVI
FIGURE 10A. START CONVERSION
DATA IS VALID IN
OUTPUT LATCHES
INTR
ASSERTED
1/2 fCLK
INTR
CS
RD
DATA
OUTPUTS
INTR RESET
tRI
VALID
DATA
tACC
THREE-STATE
(HI-Z)
t1H , t0H
VALID
DATA
FIGURE 10B. OUTPUT ENABLE AND RESET INTR
6-11

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